JPH03263369A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide the consistency for control of the threshold voltage value of a main transistor by controlling the current between the first source and a drain and the current between the second drain and a common region by a gate, which is formed at the neighboring part to the first and second channel regions. CONSTITUTION: An N-channel 38 is controlled by a gate 42. The gate 42 controls the current between a drain region 46 and a source region 48. These parts constitute a body transistor 58. In general, the drain region 46 is connected to a reference voltage, and the fixed voltage is supplied to a channel region 34 when the body transistor is on. When a transistor 56 is on, the channel region 34 is floated, and the increased driving current can be used for the circuit, including the transistor 56 in this design. When the transistor 56 is off, the channel region 56 is connected to the reference voltage. The threshold voltage, having consistency which can measure the transistor 56 in the circuit including the transistor 56 is useful for the accurate operation, is obtained.

Description

[Detailed description of the invention] "Industrial application field" TECHNICAL FIELD This invention relates to integrated circuit manufacturing.

More particularly, the present invention relates to fabricating transistors in an insulator top half.

``Prior Art'' Semiconductor-on-insulator structures often emit radiation! ) Used in applications requiring resistance to the J-ray effect. A semiconductor-on-insulator structure includes a single crystal semiconductor layer, usually silicon, formed on an insulating structure such as sapphire or silicon dioxide. This monocrystalline layer is typically divided into discrete regions or menas, so as to provide complete electrical isolation between components formed in one mesa and those formed in the other mesa. There is. Insulator - [Semiconductor structures are resistant to radiation effects due to the isolation of electrical devices from the substrate. When radiation particles, such as Arnor (alpha) particles, are applied to a conventional integrated circuit, errors occur in the operation of the integrated circuit due to the interaction between the electrical devices and the substrate. In semiconductor-on-insulator structures, this interaction is prevented due to the insulating layer.

One problem with using semiconductor-on-insulator structures is the body effect (b) on the channel of a field effect transistor.
ody effect). Field effect transistors operate by coupling a voltage to the channel, thereby causing conduction between the source and drain regions. The point at which conduction occurs between the source and drain is called the threshold voltage. Because the channel is formed in an insulated structure, trapped charge can lead to changes in the threshold voltage, which can lead to inconsistent operation of the field effect transistor. A common technique to avoid this effect is to provide a ground contact in the channel. However, floating channel region effects are not all negative. For example, due to the floating channel region, a larger drive current through the channel can be obtained. This allows faster operation of integrated circuits using transistors with larger drive currents. The present invention addresses floating of the channel region during the "on" state of the transistor when a larger drive current is useful, and when the transistor is to be turned off to obtain a consistent threshold voltage. The object is to obtain a structure and method adapted to supply a control voltage on a channel.

SUMMARY OF THE INVENTION 1 Embodiments of the invention disclosed herein provide structures and methods for actively controlling the voltage applied to the channel of a field effect transistor. , a transistor is fabricated that is connected to the channel region. The channel transistor is of the opposite conductivity type to the transistor that utilizes the main channel region. The source of the channel transistor is connected to the channel, and the drain of the channel transistor is connected to the base. The same gate is used to control the channel transistor and the main transistor.

On the side where the voltage that makes the main transistor conductive is applied,
The channel transistor is non-conducting, leaving the channel floating and allowing a larger drive current. On the other hand, when a voltage is applied that turns off the main transistor,
The channel transistor turns on, fixing the channel region to the reference voltage. This results in consistent threshold voltage control of the main transistor.

In one preferred embodiment, the channel of the main transistor is used as the source of the channel transistor, and the gate of the main transistor extends over the channel region of the channel transistor. A reference voltage is connected to a drain region formed on the channel region of the channel transistor on the side opposite to the channel of the main transistor. In another preferred embodiment, the drain region is located adjacent to the source region of the main transistor. Many non-paths (no
n-pass) In a transistor circuit, the source of the main transistor (which is fixed) is connected locally to each other, making for a simpler interconnection. 411! can give structure.

Embodiment FIG. 1 is a plan view of one embodiment of the present invention. Second
FIG. 1 is an electrical circuit diagram showing the operation of the embodiment shown in FIG. 3A and 3B show the Wii side of the embodiment shown in FIG. 1. Figures 4A to 4 are schematic side views showing the manufactured culm of the embodiment shown in Figure 1.

The embodiment shown in FIG. 1 includes two coupled transistors. The first transistor is the main transistor 56 and the second transistor is the body or channel transistor 58. This structure is the insulating layer 1
It is formed in the shape of a mesa 14 on 2. Insulating layer 12 may be silicon dioxide or any other insulating structure known in the art. The gate 42 is connected to the main transistor 5
The current between the source 54 and drain 52 of 6 is 1lill@
do.

Source 54 and drain 52 are coupled to other devices to perform the function of field effect transistors in integrated circuits that include this embodiment of the invention. Goo h 42 controls the current flowing through channel region 34 and thereby controls the current from drain 52 to source 54 . The channel region 34 is a p-type region and is formed to be self-aligned with the regions 1 to 42. Since the P+ source I region 48 has the same conductivity type, it is electrically connected to the channel region 34. N-channel 38 is controlled by gate 42, which controls current flow between drain region 46 and source region 48. These parts constitute a body transistor 58. Generally, the drain region 46 is connected to a reference voltage and the body transistor 5
8 supplies a fixed voltage to the channel region 34 when it is on. The structure of FIG. 1 is designed so that when transistor 56 is on, channel region 34 floats and increased drive current is available for the circuitry that includes transistor 56. When transistor 56 is off, channel region 34 is coupled to a reference voltage;
A uniform threshold voltage is obtained that is useful for predictable and accurate operation of transistor 56 in circuits that include transistor 56.

FIG. 2 is an electrical circuit diagram showing the electrical operation of the structure shown in FIG. M1. Source region 54 and drain region 52 are coupled to other devices in the integrated circuit.

Gate 42 controls both transistor 56 and transistor 58. Source region 48 is coupled to channel 34 of transistor 56. Drain region 46 is coupled to a reference voltage. In this embodiment, transistor 5
6 is an n-channel transistor, and transistor 58
is a pft channel transistor. While the high voltage C: is applied to the gate 42, the transistor 58 is off;
Transistor 56 is on. This allows the channel region to float above the run raster 56. While a low voltage is applied to gate 42, transistor 58 is on and transistor 56 is off. Since transistor 58 is on, the voltage level on channel region 34 is controlled by the reference potential connected to drain region 46 .

Figures 3A and 3B are lines AA and 1 of Figure 1, respectively.
38 is a cross-sectional view along line 38. As can be seen from FIG. 3A, an insulating layer 12 is formed on the surface of the substrate 10.

In this particular embodiment, substrate 10 is a single crystal silicon substrate and insulating layer 12 is a silicon dioxide layer formed by oxygen ion implantation. Oxygen ion implantation method (SIM)
OX) is described in U.S. Patent No. 3,855.00.
No. 90 and No. 4.241.359. Sidewall oxide regions 28 are provided on the sidewalls of mesa 14 to stabilize conduction at the surface of the ends of the mesa. Gate 42 is isolated from channel regions 34 and 38 by silicon dioxide layer 30. The gate 42 is the third A
As shown, the conductivity between source region 48 and drain region 46 is controlled. Game i~42 also has 3rd B
As shown, the conductivity between source region 54 and drain region 52 is controlled.

Figures 4A-4 are schematic side views corresponding to Figure 3, illustrating the manufacturing steps required to make the embodiment shown therein.

Oxygen ions are implanted into single crystal silicon substrate 10 and annealed to form insulating layer 12.

Next, an epitaxial layer 14 is formed on the short crystal silicon structure remaining on the silicon dioxide layer 12 as a seed region for nucleation. The substrate 10 and thus the epitaxial layer 14 may be an n- or p-type layer using, for example, a 100 crystal orientation. The doping concentration is 3 to 6 ohm centimeters for n-type and 10 to 12 ohm centimeters for p-type. The steps described here assume that epitaxial layer 14 is n-type.

A silicon dioxide layer 16 is then grown to a thickness of approximately 350 angstroms using thermal oxidation techniques. next,
Silicon nitride layer 18 is deposited by low pressure vapor deposition to a thickness of approximately 1.700 angstroms. Next, about 30% of
．． Silicon dioxide layer 2 to a thickness of 200 angstroms
A photoresist layer 22 is then applied on the surface of the silicon dioxide layer 20.

Photoresist layer 22 using known lamination techniques
is exposed and processed. Using photoresist layer 22 as an etch mask, silicon dioxide layer 20, silicon nitride layer 18, and silicon dioxide layer 16 are etched. Layer 16.18.20 is etched using reactive ion etching 2 techniques well known to those skilled in the art for exhibiting isotropic etch characteristics.

Photoresist layer 22 is then removed using conventional wet removal techniques. Next, for the structure in Figure 4B, 2
Step ion implantation is performed. The first step is to implant elementary ions with an energy of about 30 kiloelectron volts to a density of about 3 x 1012 ions/cm2. In the second step, boron ions with an energy of about 80-1 = roelectron volts are
The method is to implant at a density of x1012 ions/ClR2. As a result, a channel stop region 14' is formed as shown in Figure MS4B. The silicon dioxide 1ii20 is then removed using any etch technique such as deglaze using hydrofluoric acid. Next, using a low-pressure vapor deposition method, about 1,000
A silicon dioxide layer 24 is deposited to a thickness of 0 angstroms. The silicon dioxide layer 24 is then etched using an anisotropic etching process, such as reactive ion etching (such as carbon tetrachloride) with chlorine as a base gas, as shown in FIG. 4D. A sidewall oxide region 26 is formed.

Next, the silicon nitride layer 18, the silicon dioxide layer 16, and the sidewall silicon oxide layer 18 are formed on the epitaxial silicon layer 1.
It is used as an etch mask for etching step 4. Epitaxial silicon layer 14 is etched using reactive ion etching with hydrochloric acid, resulting in the structure shown in Figure 4E.

FIG. 4E includes a sidewall insulation layer 14' that prevents unwanted conduction along the edges of mesa 14.

Formation of such a sidewall protective layer is described in Hajloubi, June 28, 1988, assigned to the assignee of the present application.
No. 4,753,896 to An. The structure of FIG. 4E is then oxidized to install approximately 250 Angstroms of silicon dioxide on the sidewalls of mesa 14. Additionally, a silicon dioxide layer approximately 2,500 angstroms thick was deposited by low pressure vapor deposition and etched by reactive ion etching to form the fourth F.
A sidewall silicon dioxide layer 28 as shown in the figure is obtained. In the following drawings, the protected area 14' has been omitted from the drawings for clarity.

The silicon nitride layer 18, silicon dioxide@16, and sidewall regions [26] are removed by a two-step etching process. That is, silicon nitride layer 18 is etched using hot phosphoric acid, and silicon dioxide layer 16 and sidewall silicon dioxide layer 26 are removed by anisotropic etching in a fluorine-based chemical atmosphere. Due to the anisotropic nature of the reactive ion etch, silicon dioxide layer 28 remains.

Next, the silicon dioxide layer 30 is grown by thermal oxidation of the surface of the mesa region 14, as shown in FIG. 4G.
A silicon dioxide layer 30 is obtained. Photoresist layer 32 is then applied and patterned using conventional photolithography techniques to obtain the structure of photoresist 1132 shown in FIG. 4G. Next, for the structure shown in Figure 4G, a 2 boron ion with an energy of about 80 kiloelectron volts has a density of about 3.5X10 ions/cm.
Ions are implanted to a density of 2. This sets the backside threshold voltage of p region 534 to 25 volts or more. In addition, adjustment of the front threshold voltage of the ρ region IJli34 allows boron ions with an energy of about 25 kD electron volts to be adjusted to a density corresponding to the selected threshold voltage.
This is done by ion implantation. The edges of photoresist layer 32 are chosen to fall within region Δ, which is the overlap region in which p+ resource region 48 is formed. Since the p+ region 48 is formed in this region, the alignment of the 7 photoresist within the region Δ is not exact.

Next, the photoresist 1fij32 is removed and the 40th
As shown in the figure, a second) A Trogis 1 layer 36 is applied;
patterned. Next, for the structure in Figure 40,
A boron ion with an energy of about 25 kiloelectron volts has an energy of about 1. A density of OX120 ions/an'' is implanted, which sets the front threshold voltage to about -1 volt. Next, a phosphorus ion with an energy of about 180 kiloelectron volts, about 1.0 volts, is implanted. A second ion implantation 6 with a density of 22 X 10 ions/cm 2 is performed, setting the backside threshold voltage to approximately −13 volts. The combination of energy and density of is selected to obtain specific properties in a specific environment. In the structure shown in Figure 41-1, this ion implantation is performed between n-channel region 38 and p-channel region 34. A void 40 is left in the space.

This is an area within the area Δ shown in FIG. 4G,
N-channel region 38 and p-channel region 34 overlap without creating a gap or having an adverse effect on the operation of the integrated circuit, as shown in FIG.

Photoresist layer 36 is then removed, silicon dioxide layer 30 is stripped, and a second silicon dioxide layer 31 is formed using thermal oxidation techniques to a thickness of approximately 250 Angstroms. Next, the polycrystalline silicon layer 42 has a thickness of about 4,50 mm.
0 angstroms thick and patterned to yield the structure shown in FIG. A photoresist layer 44 is then applied and patterned as shown in FIG. 4J. Next, for the structure shown in Figure 4J, boron ions with an energy of about 20 kiloelectrets [1 mvolt] are about 2 x 1015 ions/cm2.
The density of ions is implanted. Through this ion implantation,
As shown in FIG. 4J, a source region 48 and a drain region 46 are formed. Next, the photoresist layer 44 is removed and a photoresist layer 50 is left on the surface of this 1i3Th, fourthly as shown in the figure. next,
Fourth, phosphorus ions with an energy of about 140 kiloelectron volts are implanted into the structure shown in the figure at a density of about 5 x 1014 ions/cttr2, and then about 150
Arsenic ions with an energy of kiloelectron volts have a density of approximately 3.5×10 ions/cIl+2,
Ions are implanted. Through these ion implantations, a source region 54 and a drain region 52 are formed as shown in FIG. In this way, the embodiment shown in FIG. 1 is produced.

A plan view of the second preferred embodiment is shown in FIG. An electrical circuit diagram illustrating the operation of the embodiment shown in FIG. 5 is shown in FIG. Cross-sections taken along lines AA and BB are shown in Figures 7Δ and 7B. The manufacturing steps necessary to produce the example shown in FIG.
This is shown in Figure A and Figure 8B.

The embodiment of FIG. 5 includes two transistors, a main transistor 156 and a body transistor 158. In the main transistor 156, the gate 142 is connected to the source 1
54 and the drain 152. This provides control by controlling the conductivity of the channel region 134. Channel region 134 is adjacent to n-channel region 148.

P channel region 134 functions as the source of the body transistor, and p+ region 146 functions as the drain. The conductivity between p-channel region 134 and p+ drain region 146 is controlled by gate 142 by controlling the conductivity of n-channel region 148. This makes the body transistor aIR.

An electrical circuit of the structure shown in FIG. 5 is shown in FIG. Gate 142 is connected to n-channel transistor 156 and p
Controls the conductivity of channel transistor 158. When a high voltage is applied to gate 142, p-channel transistor 158 is turned off and n-channel transistor 156 is turned on. With p-channel transistor 158 off, channel region 134 is allowed to float and maximum drive current is provided by transistor 156. When a low voltage signal is provided to gate 142, the p-channel transistor is turned on and the n-channel transistor 156 is turned off. Since p-channel transistor 158 is on, channel region 134
is fixed to a reference voltage, a constant threshold voltage, and controllable on/off characteristics are provided by transistor 156.

Figures 7A and 7B refer to AA and BB in Figure 5, respectively.
FIG. As can be seen from Figure 7A,
Gate 142 controls the conductivity of channel region 148 and thus between p-region 134 and p-to region 146. As can be seen in FIG. 7B, gate 1-142 also controls the conductivity of p-region 134, thereby controlling conductivity 13m between source region 154 and drain region 152.

FIG. 8A is a side view showing an intermediate step for manufacturing the embodiment shown in FIG. 5. Figure 8A corresponds to the steps shown in Figure 4G, and the steps used to create the structure shown in Figure 4G are also used to create the structure shown in Figure 8A. 8A, where reference numerals corresponding to the parts in FIG. 4G plus 100 are given to the corresponding parts in FIG. Corresponds to area 28>.

The structure in Figure 8A has an energy of about 180 kiloelectron volts and about 1.2 x 1012 ions/cm
A first ion implantation of phosphorous ions is performed at a density of 2.2. This allows adjustment of the backside threshold voltage and, to some extent, the frontside threshold voltage. The plane threshold voltage also has an energy of about 25 kiloelectron volts, and about 1.45X1012 ions/
The density of an 2 is adjusted by implanting boron ions. Next, a photoresist layer 132 is applied,
The pattern is processed as shown in FIG. 8B. Next, the eighth
The structure in diagram B has an energy of about 85 kiloelectron volts and contains about 3.7X1012 ions/cm2
Boron ion implantation is performed at a density of . This is ntl
The backside threshold implant used to form A-region 138 is canceled. To adjust the front-side threshold voltage of p-region 134, boron ions with an energy of approximately 25 kiloelectronvolts are implanted. , a density selected to obtain the desired threshold voltage, may be additionally implanted.
132 is then removed. The silicon dioxide layer 130 is
Any silicon dioxide etching method can be used to etch, such as reactive ion etching in a fluorine-based chemical atmosphere.

2 Next, using thermal oxidation, about 250
Thermal growth of the gate oxide is performed to a thickness of angstroms. Next, a polycrystalline silicon layer 142 is applied and patterned, as shown in Figure 8C. Next, a layer of photoresist 136 is applied over the surface of the patterned pad 142 and patterned to obtain the structure shown in FIG. 8C. Next, for the structure in Figure 8C,
An implant of boron ions with an energy of about 20 kiloelectron volts and a density of about 2x10 ions/α2 is performed to form a p-do region 146 as shown in FIG. 8C. Next, photoresist layer 136
is removed, a photoresist layer 150 is applied,
The pattern is processed as shown in FIG. 8D. 8th D
The structure shown is then subjected to an ion implantation of phosphorus with an energy of about 140 kiloelectron volts and a density of about 5 x 10 ions/IJ2, and an ion implantation of phosphorus with an energy of about 150 kiloelectron volts and a density of about 3 A second ion implantation of arsenic ions at a density of .5.times.10.sup.15 ions/ClR.sub.2 is then performed to form n+ source and drain regions, 154 and 152, as shown in FIG.

9 and 10 are plan views of another preferred embodiment of the invention. In FIG. 9, main transistor 256 includes drain 252, source 254, channel 234 regions, and gate 242. In FIG. The channel transistor includes a main channel 234, a channel transistor channel 248, and a channel transistor drain 246. In addition to a more compact arrangement,
The structure of FIG. 9 has a channel transistor drain 246 and a main transistor source 254 formed adjacent to each other. In many circuits, the source 254 of the main transistor and the drain 246 of the channel transistor are tied to the same reference voltage. The structure of Figure 9 allows these regions to be easily connected together by silicide layers of titanium, molybdenum, or other refractory metals, or by local interconnections such as titanium nitride phase q-connections. ing. This allows for a very compact structure by limiting the necessary connections to the transistors. In FIG. 10, main transistor 3
56, drain 352, source 354, channel 33
4 and a gate 342. The channel transistor includes a main channel 334, a channel transistor channel 348, and a channel transistor drain 3.
Contains 46. The structure of FIG. 10 has the same features but is a slightly more compact arrangement than the structure of FIG.

Having described herein specific embodiments of the invention,
They are not intended to limit the scope of the invention. It will be apparent to those skilled in the art from ms Paddy that numerous modifications to the invention are possible. For example, it is possible to use transistors with conductivity type characteristics opposite to those shown in the specification or regions of opposite conductivity type. Furthermore, the @ structure used here can be applied to structures other than silicon-on-insulator structures. For example, if a field-effect transistor is formed in an isolated well in a B i CMO8 integrated circuit, or if the well is completely separated by a buried region under the door, this Sophisticated contact schemes could be used to advantage. The scope of the invention is limited only by the claims.

Regarding the above description, the following sections are further disclosed.

(1) A semiconductor device, comprising: a substrate having a first conductivity type; a first source region having the first conductivity type formed in the substrate; a first source region formed in the substrate; A drain region,
a common first channel region and a second source region having the first conductivity type and spaced from the first source region and defining therebetween a common first channel region and a second source region of a second conductivity type; ,
a first drain region, a second channel region formed adjacent to the common region and having the first conductivity type; a second channel region formed adjacent to the second channel region and having the second conductivity type; 6 a gate formed adjacent to the first and second channel regions, the gate having a current between the first source and drain regions and the second drain and the common gate; the current between the first and second channel regions is controlled such that when one of the first and second channel regions is non-conducting, the other is conducting, and when the two channels are conducting, the other channel is non-conducting. A semiconductor device that includes a gate that is controlled to become conductive.

(2) The device according to item (1), wherein the substrate is formed on an insulating layer.

(3) The device according to item (2), wherein the substrate is electrically isolated from other components formed on the same insulating layer-1.

(4) The device according to item (3), wherein the substrate includes a mesa structure.

(5) The device of paragraph (1), wherein the substrate includes crystalline silicon.

(6) The device of paragraph (1), wherein the second drain region is coupled to a reference voltage.

7 (7) The device of paragraph (1), further comprising a dielectric layer sandwiched between the substrate and the first and second channel regions.

(8) The device according to item (1), wherein the second drain region is formed adjacent to the second channel region and the first source region.

(9) The device according to item (8), wherein the first sos region and the second drain region are electrically connected.

(10) The device according to item (9), wherein the electrical connection between the first source region and the second drain region is made of conductive silicide.

(11) The device according to item (1), wherein the first conductivity type is N type and the second conductivity type is P type.

(12) The device of paragraph (1), wherein the second channel region is not common to either the first source region or the first drain region.

(13) The semiconductor device according to item (1), wherein the first source region, the first drain region, and the eighth channel region are all formed at the same depth in the substrate. Device.

(14) A method for manufacturing a semiconductor device, comprising: providing a substrate having a first conductivity type; and forming a first source region having the first conductivity type in the candy substrate. forming a first drain region having a first conductivity type in the substrate, the drain region being spaced from the first source region, and a second drain region formed therebetween; forming a first drain region adjacent to the common region to define a common first channel region and a second source region having a conductivity type of; forming a second drain region having the second conductivity type adjacent to the second channel region; forming adjacent groups 1 to 1, wherein the gate controls current between the first source and drain regions and between the second drain and the common region; 1st
and the second channel region so that when one channel is non-conductive, the other channel is made conductive, and when one channel is conductive, the other channel is made non-conductive. A method including forming.

(15) The device manufacturing method according to item (14), wherein the substrate is formed on an insulating layer.

(16) The device manufacturing method according to item (15), wherein the substrate is electrically isolated from other components formed on the insulating layer.

(17) The device manufacturing method according to item (16), wherein the substrate includes a mesa 1g structure.

(18) The device manufacturing method according to item (14), wherein the substrate includes crystalline silicon.

(19) The device manufacturing method according to item (10), further comprising the step of connecting the second drain region to a reference potential.
Method.

0 (20) The device manufacturing method according to item (14), further comprising the step of forming a dielectric layer sandwiched between the gate and the first and second channel regions.

(21) The apparatus according to item (14), further comprising the step of forming the second drain region adjacent to both the second channel region and the first source region. Including, methods.

(22) The method according to item (21), wherein the first conductivity type is N type, and 1) the second conductivity type η is P type.
Method.

(23) The method of paragraph (14), further comprising forming an electrical interconnect between the first source region and the second drain region.

(24) The method of paragraph (23), wherein the electrical interconnect is a conductive silicide layer.

(25) The described embodiments of the invention provide structures and methods for actively controlling the voltage applied to the channel of a field effect transistor. In the embodiments described herein, a transistor is created that is connected to a channel region. This channel transistor 258 has the opposite conductivity type from transistor 256, which uses a main channel region. channel] The source of transistor 258 is connected to channel 234;
The drain 246 of channel transistor 258 is coupled to a reference voltage.

The same gate i-242 is used to control channel transistor 258 and main transistor 256. When a voltage is applied that turns on main transistor 256,
Channel transistor 258 is turned off and channel 2
34 floating and allows a large drive current. On the other hand, when a voltage is applied that turns off transistor 256, channel 1 to transistor 258 turns on, fixing channel region 234 to the reference voltage.

This allows consistent threshold voltage control of main transistor 256.

In another embodiment 85, channel 234 of main transistor 256 is used as the source of channel transistor 258, with main transistor gate 242 extending over channel region 248 of channel transistor 258. A reference voltage is then coupled to a drain region 246 formed on the opposite side of the channel region 248 of the channel transistor from the main transistor channel 234 .

In a preferred embodiment, channel 248 of channel transistor 258 is formed below main transistor gate 1242 and drain region 2 of channel transistor 258.
46 is formed at the corner of the region where the source 254 of the main transistor 256 is formed. This results in a more compact arrangement, and the source 2 of main transistor 256.
54 can be shorted to the drain 246 of channel transistor 258. This allows for a very compact arrangement 4q, and this method can be used since the sides of the main transistor, which is the source, are often fixed when cutting into transistors other than the pass transistor.

[Brief explanation of drawings]

FIG. 1 is a plan view of one embodiment of the present invention. FIG. 2 is an electrical circuit diagram illustrating the operation of the structure of FIG. 3A and ff13B are cross-sectional views taken along lines AA and 8B, respectively, in FIG. 1. Figures 4A-4 are schematic side views showing the processing steps necessary to fabricate the embodiment shown in Figure 1. FIG. 5 is a plan view of one preferred embodiment of the present invention. FIG. 6 is an electrical circuit diagram showing the electrical operation of the embodiment of FIG. 5. Figures 7A and 7B are AA and B, respectively, of Figure 5.
FIG. FIGS. 8A to 8D are schematic cross-sectional views that do not show the process steps necessary to fabricate the embodiment shown in FIG. 5. FIGS. 9 and 10 are plan views of preferred embodiments of the present invention. "Reference number" 3!1 10... Substrate 12... Insulating layer 14... Mesa 16... Silicon dioxide layer 18... Silicon nitride layer 20... Silicon dioxide layer 22... Photoresist Layer 24...Silicon dioxide layer 26...Side wall silicon dioxide layer 28...Side wall decoction silicon layer 30...Silicon dioxide layer 32...Photoresist layer 34...Channel region 36... Photoresist 1 to layer 38...N channel region 40...Gap 42...Polycrystalline silicon gate 44...Photoresist layer 46...Drain region 48...Source region 5 242... Gate 246...Drain region 248...Channel region 252...Drain region 254...Source region 256...Main transistor 258...Channel transistor 334...Main channel 342...Gate 346... ...Drain region 348...Channel region 352...Drain region 354...Source region 356...Main transistor

Claims (2)

[Claims] (1) A semiconductor device, comprising: a substrate having a first conductivity type; a first source region having the first conductivity type formed in the substrate; a first source region having the first conductivity type formed in the substrate; A drain region,
a common first channel region and a second source region having the first conductivity type and spaced from the first source region and defining therebetween a common first channel region and a second source region of a second conductivity type; ,
a first drain region, a second channel region formed adjacent to the common region and having the first conductivity type; a second channel region formed adjacent to the second channel region and having the first conductivity type;
a second drain region having a conductivity type, and a gate formed adjacent to the first and second channel regions, wherein the current between the first source and drain regions and the second drain region are controlling the current between the common area and the common area;
When one of the first and second channel regions is non-conductive,
1. A semiconductor device comprising: a gate controlling the other channel so that the other channel is conductive, and when the one channel is conductive, the other channel is non-conductive. (2) A method for manufacturing a semiconductor device, the method comprising:
providing a substrate having a conductivity type of
forming a first source region having a first conductivity type; forming a first drain region having a first conductivity type in the substrate, wherein the drain region is connected to the first conductivity type; forming a first drain region spaced apart from the source region and defining a common first channel region and a second source region having a second conductivity type therebetween; , forming a second channel region having the first conductivity type adjacent to the common region; a second drain having the second conductivity type adjacent to the second channel region; forming a gate adjacent to the first and second channel regions, the gate being between the first source and drain regions and between the second drain and the second channel region; A current between the common regions is controlled so that when one of the first and second channel regions is non-conductive, the other is made conductive, and when the one channel is conductive, the other channel is made non-conductive. A method comprising forming a gate to control the gate.