JPH03261217A - Delay circuit - Google Patents

Abstract

PURPOSE:To easily change a delay by using a 2-port RAM to suppress the increase in the number of gates due to the increase in the delay. CONSTITUTION:This circuit consists of a counter circuit 4 generating an initial address data, a decoder circuit 5 receiving an initial address data to designate an address of a 2-port RAM 8 and a delay element 6 to prevent a spike of the decoder circuit 5 from giving effect on write address designation of the 2-port RAM 8. Moreover, the circuit is provided with an AND gate 7 receiving output signals from the decoder circuit 5 and the delay element 6 as input signals and the 2-port RAM 8 receiving data from the decoder circuit 5, the AND gate 7 and outputting a data with an optional delay. Then the address of the 2-port RAM 8 is designated by a clock input 1. Thus, the increase in number of gates is minimized and the delay circuit whose delay time is easily change is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a delay circuit in which the amount of delay can be easily changed and an increase in the number of gates can be minimized even if the amount of delay increases. It is related to.

[Conventional technology] Figure 3 shows, for example, the 85 Mitsubishi semiconductor bipolar digital
It is a circuit diagram of an 8-bit shift register (M74LS166AP) shown in L'IC<LSTTL> edition.

In the figure, (1a) is a clock input, (1b) is a clock inhibit input used as a clock enable or clock inhibit function, (3a) to (3h) are parallel data inputs, (9) is a data output, and (10) is a clock input. Load input, (11
) is serial data input, (12) is direct reset input, (
13) is the clock input (la) and the clock inhibit input (
1b), (14) is the driver, (15a) to (15k) are the inverters, (16)
a) - (16p) are AND gates whose input signals are a data input signal and a load signal, (17a) - (17h)
is a NOR gate that selects serial input or parallel input, (18a
) to α8h) are flip frogs.

Next, the operation will be explained. Parallel input or W nJ
The input mode can be selected by the signal at the load input (10). That is, when the load input (10) is at the "H" level, the serial data input (11) is activated, and the 8-bit flip-flops (18a) to (18h) perform serial S/aft by clock pulses.

Further, when the load input (10) is at the "L" level, the parallel data inputs (38) to (3h) are activated, and the input data is loaded in synchronization with the next clock pulse. Serial data transfer is inhibited while parallel loading is being performed. The clock operates by shifting or loading at the rising edge of the clock pulse from the rLJ level to the "H" level.

When the clock inhibit input (1b) is held at the "H" level, the clock operation is stopped, and when it is set at the "L" level, data transfer is enabled. The clock inhibit input (lb) can be changed to the "H" level only while the clock input (18) is at the rHJ level. Directly connected reset input with buffer (
12) operates with priority over all other inputs and resets the shift register.

[Problem to be solved by the invention] Since the conventional delay four-way is configured as described above,
As the amount of delay increases, the number of stages of the shift register also increases, resulting in an increase in the number of gates.

This invention was made to solve the above problems, and aims to provide a delay circuit that can minimize the increase in the number of gates and easily change the amount of delay. purpose.

[Means for Solving the Problems] A delay circuit according to the present invention includes: a counter circuit that generates initial address data; a decoder circuit that inputs the initial address data to specify an address of a two-port RAM;
a delay element to prevent spikes in the decoder circuit from affecting write addressing of the 2-port RAM;
an AND gate whose input signals are the output signals of the decoder circuit and the delay element;
It is equipped with an ND gate and a two-port RAM that inputs data and outputs data delayed by an arbitrary amount of delay.

[Operation] The counter circuit according to the present invention specifies the address of the 2-port RAM by inputting a clock.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The first figure is a block diagram of a delay circuit.

In the figure, (1) is a clock input, (2) is a reset input, (3) is a data input, (4) is a counter circuit that generates initial address data, and (5) is a circuit that inputs the above initial address data. , 3T○8 decoder circuit that generates the address of 2-port RAM4 (8), (6) is a delay to prevent the spike of the decoder circuit (5) from affecting the write address specification of 2-port RAM (8). Motoko, (7
) is the output signal of the decoder circuit (5) and the delay element (6
) and an AND gate whose input signal is the output signal of (9)
The 52-port RAM (8) which is a data output uses the output signals of the decoder circuit (5) and the AND gate (7) and data as input signals and outputs data delayed by an arbitrary delay amount.

FIG. 2 is a timing chart showing signal waveforms at various parts of the circuit shown in FIG. 1.

Next, the operation will be explained.

Before the automatic operation, the 3-bit counter circuit (4) is initialized to 0 (Hex) by inputting the reset input (2).

Clock input (1) CL H sets the count value of the 3-bit counter circuit (4) to 1, and the output signal of the 3TO8 decoder circuit (5), which uses the output signal as an input signal, causes the 2-port RAM (8 ) reads the 8-bit data at address 1 on the read side and outputs the data (
9). At the next clock input (1) CLK, the count value of the 3-bit counter circuit (4) becomes 2, and the data at address 2 is read out in the same way. This operation is repeated sequentially, and after reading the data at address 7, data is read sequentially from address 0.

Clock input (1) CLK is the delay element (
6), and after a certain period of time delay, a write-side address signal with no spikes is generated by logic accumulation with the output signal of the decoder circuit (5) of 3-08, and the 2-hode RAM (
8) Write 8-bit data to address O on the write side and hold it. Next clock input (1) 3 at CLK
The counter value of the bit counter circuit (4) becomes 2,
Similarly, data is written and held at address 1. This operation is repeated in sequence, and after writing data to address 7, it returns to address 0 and writes and holds the data.

In this way, this circuit can be used, for example, as a 2 baud) RAM (8)
Since the write address is connected to an address 1" before the read address, such as read address 1 and write address 0, the clock input (
1) CLH reads data at read address 1 and writes data to write address 0. In other words, the data written to write address 0 is read from read address 7 in order from read address 1.
The next value υ that is read at the address will be output incorrectly at certain times.

In the above embodiment, the delay element (6) was used to prevent spikes from appearing in the write signal of the 2-port RAM (8), but it is also possible to adopt a configuration in which no spikes appear from the output of the decoder circuit (5). For example, the delay element (6) may not be used.

Keita, above l! In the example, a 3-bit counter circuit (4
), a 3 to 8 decoder circuit (5), and an 8 word x 8 bit 2-port RAM (8), but the same effect can be obtained by using any arbitrary one.

〔Effect of the invention〕

As described above, by using a two-port RAM, the present invention can suppress the increase in the number of gates due to an increase in the delay amount of this circuit to the necessary minimum, and can easily change the delay amount. It has the effect of being able to

[Brief explanation of drawings]

Section 1 is a block diagram of a delay circuit showing an embodiment of the present invention. Fig. 2 is a timing chart showing the signal waveforms of various parts applied to the circuit of Fig. 1. Fig. 3 is a block diagram of a conventional 8-bit shift register. FIG. In the figure, (1) is a clock input, (2) is a reset input, (3) is a data input, (4) is a counter circuit, (
5) is a decoder circuit, (6) is a delay element, (7) is an AND game), (8) is a 2-port RAM, (9)
are data outputs, and the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Claims] A counter circuit that generates initial address data by inputting a clock signal, a decoder circuit that inputs the above initial address data and specifies the address of the 2-port RAM, and a decoder circuit that uses the clock signal as an input signal to prevent spikes in the decoder circuit. a delay element for preventing the write addressing of the 2-port RAM from being affected; an AND gate whose input signals are the output signal of the decoder circuit and the output signal of the delay element; and the output signal of the decoder circuit and the output signal of the delay element. Input the AND gate output signal and data,
2-port RA that outputs data delayed by an arbitrary amount of delay
A delay circuit characterized by comprising M.