JPH03250874A - Output detection method and circuit for charge coupling element - Google Patents

Abstract

PURPOSE:To improve the S/N by expanding a signal resulting from an output signal of a charge coupling element subject to band limit into a Fourier series and extracting only a component corresponding to a signal charge from the output signal. CONSTITUTION:An output detection circuit of a charge coupling element (CCD) is provided with a CCD 1, an analog low pass filter 2, a sample-and-hold circuit 3, a quantizer 4, a computing element 5 and a buffer 6. Then an output signal of the CCD 1 is subject to band limit to a component using one period of a transfer clock pulse as a fundamental wave by using the analog low pass filter 2, and the output waveform subject to band limit is expanded into a Fourier series using the transfer clock pulse frequency as the fundamental wave for each period corresponding to each picture element to obtain the Fourier coefficient of the fundamental wave component and the amplitude of the output signal of the charge coupling element is obtained from the coefficient to extract only the component corresponding to the signal charge. Thus, the output signal with improved S/N is obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a charge-coupled device output detection method for removing noise contained in the output signal of a charge-coupled device and detecting only a desired signal component with high precision. The present invention relates to circuits, and in particular to noise removal from signals from gated charge-integrating output circuits.

[Prior Art] FIG. 7 is a schematic diagram showing an example of an output circuit of a charge-coupled device (hereinafter referred to as CCD).

The second output circuit is known as a gated charge integration type output circuit, and includes a CCD transfer channel 1 formed on a semiconductor substrate, a buffer circuit 2, and a reset transistor 3.

Further, a detection diode 5 is provided near one of the transfer electrodes 4 of the CCD transfer channel 1 to detect transferred signal charges and convert them into an output voltage. Transfer lock φ1. The signal charge transferred through the transfer electrode 4 by the application of φ2 flows into the detection diode 5 every cycle of transfer lock φ1 and φ2, and changes its potential.

This potential change is taken out to the outside via the buffer circuit 2.

Furthermore, a transfer lock φ1. A reset pulse φr is applied at a period equal to φ2. When the reset transistor 3 is turned on by this reset pulse φr, the potential of the detection diode 5 is reset.

FIG. 8 is a waveform diagram for explaining the operation of the gated charge integral type output circuit described above, from time t0 to time 1. A reset pulse φr is applied until then, and when the reset transistor 3 is turned on, the potential of the detection diode 5 rises to the drain voltage of the transistor 3. Next, when the reset transistor 3 is turned off at time tl, the potential of the detection diode 5 is connected to the capacitor 7 corresponding to the sum of the detection diode 5 and the gate capacitance of the buffer circuit 2, and the gate and source of the reset transistor 3. A constant reference potential determined by two capacitances: ■. become. Next, at time t3, charge is transferred and flows into the detection diode 5, and its potential changes to obtain the output voltage Vs.

By the way, time t. While the reset I transistor 3 is conductive from to time t1, the reset I transistor 3 is turned on.
generates a certain amount of noise E.

Reference potential■. is affected by this noise E14, for example, every time the reset pulse φr is applied.

It fluctuates as ±vN, and the output S/N deteriorates. This fluctuating potential VN is the reset i sound.

In addition, the reset transistor 3 is not the only noise source, but the buffer circuit 2 is also a noise source that generates random noise. The random noise E generated by the buffer circuit 2 is called l/f noise because its amplitude is proportional to the reciprocal of the frequency f. As a method of reducing the influence of this reset noise and 1/f noise and improving the S/N, the reference potential ■ is set at time t2.

is clamped to a constant potential, and then the output voltage V
The method of sampling s is known as the double correlation sampling method (Japanese Unexamined Patent Publication No. 116374/1983).
. In addition, as a noise suppression method aiming at the same effect, the CCD output signal is passed through a bandpass filter whose center frequency is the CCD transfer lock frequency, and then synchronously detected using a carrier signal synchronized with the CCD transfer lock. A circuit for detecting the output has been proposed (Japanese Patent Laid-Open No. 63-208
Publication No. 375).

According to this circuit, a signal with an improved S/N ratio can be obtained because noise is reduced in the frequency region that is the passband of the bandpass filter.

(Problems to be Solved by the Invention) In the conventional example described above, the noise that can be removed by the double correlation sampling method is limited to the low frequency components of reset noise and 1/f noise. When trying to remove time t2 and time T,
The reference potential and the signal potential, which are clamped to a constant potential at a, are affected by mutually uncorrelated random noise, and the S/N of the output signal deteriorates. The random noise in this case is 1/f
noise and other high frequency noise components.

In other words, although the double correlation sampling method can remove the low frequency components of the reset noise ■8 and 1/f noise generated by the sensor transistor 3, it cannot remove the other components, resulting in a poor S/N ratio. It's inconvenient. In fact, C
When driving a CD at high speed, high frequency noise such as ringing greatly affects the S/H.

In addition, in the synchronous detection method using a band-pass filter, the slowly changing low frequency components that are correlated between each pixel are also suppressed by the filter, making it impossible to adequately express the gradation when handling image signals with gradation. There is this inconvenience.

Furthermore, in circuit systems that directly sample and hold waveforms,
Generally, the CCD output waveform has a shape close to a rectangular wave, so when driving at high speed, the circuit system is required to have strict frequency characteristics that take into account the rising characteristics of the waveform.

This invention can remove reset noise, high-frequency random noise, etc. contained in a CCD output signal while maintaining the gradation of the image signal, improve the S/N ratio, and alleviate the frequency characteristics of the circuit system. An object of the present invention is to provide a method and circuit for detecting the output of a charge-coupled device.

[Means to solve the problem]

The output detection method of a charge-coupled device according to the present invention receives an output signal with an amplitude corresponding to a reference potential and a signal charge every cycle of a transfer clock pulse from a charge-coupled device having a gated charge-integrating output circuit. This is a method of band-limiting the signal to a component whose fundamental wave is one period of the transfer clock pulse, expanding this band-limited signal into a Fourier series, and extracting only the component corresponding to the signal charge from the output signal. .

Further, the output detection circuit of a charge-coupled device according to the present invention has the following features:
a charge-coupled device having a gated charge integrating output circuit that outputs a signal with an amplitude corresponding to the reference potential and the signal charge every cycle of the transfer clock pulse; an analog low-pass filter that band-limits the band-limited signal to a fundamental wave component, and an AD converter that samples the band-limited signal at predetermined time intervals, quantizes it, and converts it into a digital signal;
and an arithmetic unit that expands the digital signal into a Fourier series and extracts only the component corresponding to the signal charge.

[Function] According to the present invention, the output signal of the charge-coupled device is band-limited to a component whose fundamental wave is one cycle of the transfer clock pulse,
This band-limited output waveform is expanded into a Fourier series with the transfer clock pulse frequency as the fundamental wave for each section corresponding to each pixel to obtain the Fourier coefficient of the fundamental wave component, and from this coefficient, the output signal of the charge-coupled device is calculated. By determining the amplitude, only the component corresponding to the signal charge is extracted.

Therefore, an output signal with an improved S/N ratio can be obtained in which the effects of random noise such as reset noise and 1/f noise generated by the reset transistor of the gated charge integrating output circuit are eliminated.

[Example] A method for detecting the output of a charge-coupled device according to the present invention will be described with reference to the waveform diagram shown in FIG. In addition, the first
In the figure, (a) is the reset pulse φr input to the gate electrode of the reset transistor mentioned above, and (b) is C
Transfer lock φ1 input to CD transfer electrode, Figure (C)
is the CCD1$ force signal.

Now, if the waveform section corresponding to each pixel (N pieces) of the CCD is section 1 to section N, and the period of the waveform is transferred and the period of lock φ1 is 1/f0, then n of the CCDC output signal (t)
Transfer lock frequency f with respect to time t within the (n=1.2s...,N)th interval. The Fourier expansion Vn(t) with the fundamental wave as Vn(t) = a y+o/2+Σafikcos2
πkfot+Σb, 1lls1n2πkf0t...■
becomes. The higher-order term in equation (2) is caused by random noise such as the reset noise of the lyse/node transistor mentioned above and 1/f noise.

Next, the desired CCD output signal V corresponding to the nth pixel is
n' (t) is the CCD at the nth pixel in FIG.
Corresponding to the fundamental wave r0 configuration (component of = 1 in 2) of the output voltage Vn(t), Vn' (t) = a, l+cos2πfat+b,
It is expressed as l+5in2πf, t, -...■, and its amplitude Vamp(n) is Vamp(n)=(a R,
"+l) R,") ""・-■.

That is, the amplitude Vamρ(n) of the desired CCD output signal
can be obtained from equation (2) by determining the first-order Fourier coefficients when the n-th section of the CCD output waveform is transferred and subjected to Fourier expansion at the lock frequency f, that is, the coefficients an+ and bMl of (2) and (2).

In principle, frequency components (including DC components) lower than the clock frequency f0 are also removed at the stage when formula (2) is defined.

Next, a method of extracting only the fundamental wave f00th order from equation (2) will be described. From the formula ■, the fundamental wave [. To find the Fourier coefficients of the components, use the orthogonality of the trigonometric functions shown below.

=2/T ・δmn ...■ f cos2πmft 5in2znft dt-〇 ...■ (However, δmn: Kronecker symbol, T = 1/f) And,
Consider the following integral over the interval T (t, , t+1/fol.

Then, by substituting the formula ■ into 2■ and 2■, and considering 2■ and the formula ■, C(n)=anl...■S(
n)=bMl...■.

Therefore, the amplitude of the desired CCD output signal ara p (
n) is obtained from the formula ■ and the formulas ■,■, νamp(n) =
(C(n)” ÷3 (n) 2) l/2
,,,(ffJ.

becomes.

Next, if we consider the time ahead of equation (■) as a discrete value sequence and the integral of 2 (2) and 2 (2) as Σ, we get: Vn(iΔt) = a-0/2+Σank cos2
πkfoiΔt+Σbnk 5in2πfoiΔt...■ (However, MΔt=T=1/fO).

From the above, the CCD output waveform shown in FIG.
The amplitude Vamp(n) is determined independently for each of the N pixels using equations (1) to (2). This amplitude V a m p (n) is the desired CCD output signal.

The “cos” and “sin” terms in formulas @ and @ are the frequency f. and the interval Δt are both known, so Vn(i
Δt) can be calculated as a weight function.

It is important here that the amplitude Vamρ(n) is determined independently for the N pixels.

By the way, according to the method of the present invention, as described above, frequency components lower than the transfer lock frequency f0 can be removed. However, this is within the interval corresponding to each pixel, and if the desired CCD output signal itself has a low frequency change, it is preserved. In other words, components that change slowly within each pixel section and have no correlation between pixels are removed, and components that change slowly over the entire pixel,
In other words, components that have correlation between pixels are preserved.

The same applies to components higher than the transfer lock frequency f0. This situation is shown in FIG.

In the figure, high frequency noise and low frequency noise are removed, but the original low frequency components of the signal shown by broken lines are not removed.

Further, the waveform of the CCD output signal has a shape close to a rectangular wave as shown in FIG. 1(C). That is, the transfer lock frequency f. It contains relatively large high frequency components. Therefore, when sampling is performed at the timing shown in Figure 1, the engine parts of the waveform (Vn (0), Vn (2
In the portion Δt), the sample value of the signal becomes ambiguous. This is an effect called aliasing that occurs when the signal components include components that are extremely high compared to the sampling frequency.

In fact, a square wave has an infinite frequency at its rise/fall. Therefore, in order to suppress this, the CCD output signal may be filtered by a low-pass filter that transfers the cutoff frequency and is set to the lock frequency fo to obtain a CCD output waveform as shown in FIG. C.C.
Since there should be no component higher than the clock frequency fo in the D output signal in principle, the desired information will not be lost even if it is passed through a low-pass filter.

From this point on, the frequency characteristics of the processing circuit system may be determined by considering the frequency fO.

Next, an output detection circuit for a charge coupled device according to the present invention will be described with reference to the block diagram shown in FIG.

In the figure, a CCD output signal output from a CCD 1 is filtered by an analog low-pass filter 2 having a cutoff frequency equal to the transfer lock frequency fo, high frequency components are removed, and the signal is supplied to a sample and hold circuit 3. The filter characteristics of the low-pass filter 2 are shown in FIG.

The sample and hold circuit 3 samples the input waveform at intervals Δt in each section 1 to N, as shown in FIG. 3 described above. The sampled signal is converted into a digital signal by the quantizer 4 and sent to the arithmetic unit 5. The sample and hold circuit 3 and the quantizer 4 constitute an AD conversion section.

The arithmetic unit 5 calculates C(n) and S from the above-mentioned equations
(n) is calculated, and the amplitude V acm p (n) is obtained from the above-mentioned second [phase] from C(n) and S (n), and is outputted via the buffer 6.

The calculation procedure in this calculation unit 5 will be explained with reference to the flowchart shown in FIG.

First, in order to calculate the first section 1 of N waveform sections corresponding to each pixel of CCD 1, n (n-1, 2,
. . , N) is set to the initial value "1" (step Sl).

Next, within the section, the CCD waveform is
In order to sample 1 (i=0゜1, ...,
M-1) is set to the first sampling point "0" (step 32). .

Next, the CO at the sampling point is calculated using the above formula (■).
The D output voltage Vn (iΔt) is determined and data sampling is performed (step S3).

Next, it is determined whether ri=LIJ (step S4)
. This is to judge whether or not M samplings have been completed within the section. If not, the value of i is advanced (step S5) and the CCD output voltage Vn (iΔt) of the next sampling point is calculated. (Step S3). This series of processing from steps 83 to S5 is repeated until all M samplings are completed.

When M sampling is completed, C(n) and S (
In step S6), the amplitude value Vamp(n) is calculated from the above-mentioned 2〇 (step S7), and this amplitude value Van+p(n) is output or stored (step S8).

Next, it is determined whether "n=N" (step 39).

This is to determine whether or not the calculation processing for all N waveform sections corresponding to each pixel of CCD 1 has been completed. If not, the value of n is incremented (step 5lO) and the process proceeds to step S2. Go back and process the next section. When the processing for all N sections is completed, a determination of "Yes2" is made in step S9, and the arithmetic processing ends.

[Effects of the Invention] According to the present invention, in a charge-coupled device having a gated charge integration type output circuit, the noise generated by the reseno I-h transistor and 1. The influence of random noise such as noise can be eliminated, and an output signal with an improved S/N ratio can be obtained.

In addition, aliasing caused by sampling can be suppressed,
Furthermore, the frequency characteristics of the circuit system can be relaxed, and a highly accurate signal detection system can be realized.

[Brief explanation of drawings]

1 to 3 are waveform diagrams for explaining the output detection method of a charge-coupled device according to the present invention. FIG. 4 is a block diagram showing an embodiment of the output detection circuit of a charge-coupled device according to the present invention. Fig. 5 is a characteristic diagram of the low-pass filter in Fig. 4, Fig. 6 is a flowchart for explaining the operation of the arithmetic unit in Fig. 4, and Fig. 7 is a schematic diagram showing an example of a gated charge integral type output circuit. 8 is a waveform diagram for explaining the operation of FIG. 7.

Claims (2)

[Claims] (1) Receive an output signal with an amplitude corresponding to the reference potential and signal charge every cycle of the transfer clock pulse from a charge-coupled device having a gated charge-integrating output circuit, and apply this signal to each cycle of the transfer clock pulse. A method for detecting the output of a charge-coupled device, characterized in that a component serving as a fundamental wave is band-limited, the band-limited signal is expanded into a Fourier series, and only a component corresponding to the signal charge is extracted from the output signal. (2) a charge-coupled device having a gated charge-integrating output circuit that outputs a signal with an amplitude corresponding to the reference potential and the signal charge every cycle of the transfer clock pulse; an analog low-pass filter that limits the band to a component with one pulse period as a fundamental wave; an AD converter that samples the band-limited signal at a predetermined time interval and then quantizes the sample and converts it into a digital signal; and the digital signal. 1. An output detection circuit for a charge-coupled device, comprising: an arithmetic unit that expands the signal charge into a Fourier series and extracts only the component corresponding to the signal charge.