JPH03250261A - Logic simulation model preparing method - Google Patents

Abstract

PURPOSE:To shorten time for preparing a simulation model by preparing the new simulation model from the simulation model, which is prepared from the circuit data of a logical block including parts with the existence of a change, and the simulation model of the logical block in the other part based on control information and connection information. CONSTITUTION:A simulation model 406 is provided so as to be divided for the unit of the logical block for a logic circuit before a change, and the simula tion model 406 before the change is composed of the connection information for the respective logical block levels and the control information showing capacity (lengths l1-l4) for each logical block level to occupy on the memory of a computer or address information (position). With the circuit data of the logical block with the existence of the change or a high-order hierarchy as the input, while limiting the preparation of the simulation model of the logical block only for the change logical block, the simulation model of the change logical block is prepared and based on the control information and the connec tion information, the simulation model is newly prepared. Thus, the time is shortened for preparing the simulation model.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic simulation for verifying the logic of a logic device, and relates to logic simulation suitable for shortening the creation time when building a simulation model on a computer. Concerning simulation model creation methods.

[Conventional technology]

Traditional simulation models use AND gates and OR gates.
Circuit data consisting of logic blocks composed of basic elements such as gates and their connection information is input, and the circuit data is modeled and created in a format that can be simulated on a computer's memory.

Regarding this creation method, a method for reducing the amount of memory required for the above simulation model is disclosed in Japanese Patent Application Laid-Open No. 60-1521.
22, and Japanese Patent Laid-Open No. 63-211036 discusses speeding up the simulation time in logic verification using the above simulation model.

In addition, as a method for modifying machine language circuit data,
No. 0-147880 discusses a correction method in which the circuit data of only the correction section is input and the machine language circuit data for the correction section is replaced by using a correction history record. There is no mention of the reconstruction of the area around the changed part using management information and connection information as shown in the invention.

[Problem to be solved by the invention]

When performing logic verification of a logic device, speeding up of simulation time is attempted as described in the above-mentioned prior art, but no consideration is given to shortening the creation time of a simulation model. For this reason, as the scale of logic devices increases, the time required to create a simulation model thereof continues to increase, which is a bottleneck in proceeding with logic verification of large-scale logic devices.

An object of the present invention is to reduce the time required to create a simulation model.

[Means to solve the problem]

The above purpose is to create a simulation model of the logic circuit when a part of the logic circuit to be simulated is changed, (1) a simulation model of the logic circuit before the change that can be divided into logic blocks; )
(1) Logical block level connection information, (3) (
Management information indicating the capacity (hereinafter referred to as length) and address information (hereinafter referred to as position) that each logical block level occupies on the computer's memory (hereinafter referred to as position); 4) Input the logic block in which the change exists and the circuit data of the upper layer, create a simulation model of the logic block only for the changed logic block, (5) create a simulation model of the changed logic block, and (4) create a simulation model of the changed logic block. , based on (5) (]).

This is achieved by reconstructing (2) and (3) and creating a new simulation model.

[Effect]

When a part of the logic circuit to be simulated is changed, the time T required to recreate the simulation model of the entire logic circuit can be expressed as the following sum.

T=Ts+Tk+TR Ts: Sum of simulation model creation time (tsl, ts2..., tsn) for each logic block Tk:
Management information creation time for each logical block (tkl, tk2
．． -, tkn) sum Tρ: logic block connection information creation time (n: total number of logic blocks of the logic circuit) Here, replace (5) created from the above (4) with the simulation model of (1). , and regarding (2), (4)
and (2) recreate everything based on itself. Regarding (3), only the length of the management information of the changed logical block is recalculated, and only the position of the management information of the changed logical block placed after the changed logical block is recalculated.

According to this method, it is possible to create a simulation model that reuses the simulation model before the change, without missing anything even when the connection state of each logic block changes due to changes or the length of the simulation model of the changed logic block changes. becomes. The time T' in this case is as follows.

T' = Ts' + Tk' + TQ Ts': Simulation model creation time of changed logic block (ts' 1, ts' 2.-, ts' n
Tk': Sum of management information creation times (tk'l, tk'2.-, tk'n') around changed logical blocks (n': Number of changed logical blocks 1≦n'<nn
#: Number of management information that needs to be recalculated due to changes n'<,
n'<n) In other words, T'<T, the time required to create a simulation model of the logic circuit can be shortened, and a simulation model equivalent to a completely re-created one can be created.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using FIGS. 1 to 6.

FIG. 1 shows an example of creating a simulation model from circuit data. The logic block A is composed of three basic elements, and the logic block B is composed of one basic element, and the basic elements 103 and 104 are connected via an upper layer C.

In the figure, 105 to 108 are basic elements 101 to 104, respectively.
This is a basic element table that stores functions such as AND and OR, and connection information within the logical block such as fan-in/fan-out destination addresses.

Further, reference numeral 112 in the figure is a connection information table showing the connection relationship between logical blocks A and B.

FIG. 2 is an example showing the hierarchical structure of a logic device to be simulated. 207 to 210 in the figure correspond to the logical blocks A and B in FIG. 1, and 201 to 206 in the figure correspond to the upper layer C in FIG. Further, in the figure, numerals 211 to 220 indicate the structure of circuit data of the logic device in a tree structure.

FIG. 3 is an example of the tree structure shown in FIG. 2 expressed by a simulation model.

301 to 304 in the figure are respectively logic blocks 2 in FIG.
17 to 220 simulation models, i.e.
The above-mentioned basic element table is assembled in logical block units. Further, 305, 306, and 307 in the figure are connection information tables showing the connection relationships of the logical blocks 217 to 220, and the upper layers 214, 212, and 307, respectively.
211 is supported. For example, the connection information table 305
, the corresponding upper layer 214 is the logic block 217 (simulation model 301), 2 code-8 (simulation model 3o2)
It shows that it is equipped with and connected.

FIG. 4 is an example showing an outline of a procedure for creating a new simulation model for the entire logic device shown in FIG. 2.

401 in the figure is a simulation model creation process 402
This command instructs to create a new simulation model of the entire logic device. The simulation model creation process 402 creates a simulation model 404 of a logical block from the command 401 and the circuit data 211 to 220 in accordance with the procedure described using FIG. A connection information table 405 is created, and a management information table 403 is created.
Create.

FIG. 5 is an example showing an outline of a procedure for creating a simulation model by reusing 403 to 405 in FIG. 4 when a change occurs in the - part of the logic device in FIG. 2.

501 in the figure is a simulation model creation process 402
This command instructs to create a simulation model by reusing the simulation model before the change. In the figure, 506 and 507 are the circuit data of the parts where changes have occurred, and correspond to 214 and 217, respectively.
The upper layer 506 does not include the logical block 218. The simulation model creation process 402 generates the management information table 50 from the command 501, circuit data 506, 507, and simulation model 406 before change.
3. Partially update the simulation model 504 of the logic block, recreate the connection information table 505, and create a simulation model of the entire logic device.

That is, first, a simulation model is created from the circuit data 507 of the changed logic block, and then
The connection information table 505 is re-created from the changed upper layer circuit data 506. At this time, the simulation block 504 is reconfigured by excluding the simulation block corresponding to 218 that is no longer installed in 506 and replacing it with the one created from 507. The management information table 503 is recalculated based on the following example.

(a) The length of the simulation model of the changed logic block is recalculated, and the length of other items is 403
Divert from.

(b) The position of the simulation model of each logical block is calculated as follows.

αn = Q 'n - Q n n: Order in which each logic block simulation model is placed on computer memory Qn, Ln: Length (Qn) and position (Ln) of each logic block simulation model before change fl'n , L'n: Length ((1'n) and position after change of simulation model of each logical block! (L'n)) FIG. 6 is a flowchart of the simulation model creation process 402.

First, the process 60 will be explained using FIG. 4 as an example.
1 receives circuit data 211 to 220 and a command 401, and uses all the circuit data as a simulation model creation target. In judgment 602, processing 6 is executed by command 401.
Bypass 03.

In the loop starting from process 604, the circuit data 207 to 210 of all wheel blocks are targeted for simulation model creation by decision 605, and in process 606, a 9-decision 607 is made to newly create the simulation model 404.
Then, the process moves to process 609, and the management information table 403 is
Create a new one.

Next, the example shown in FIG. 5 will be explained. In process 601, changed circuit data 506, 507 and command 501 are received,
Only 506 and 507 are targeted for simulation model creation. In judgment 602, processing 6 is executed by command 501.
At 03, the simulation model 406 before change is received. In the loop starting from process 604, all wheel blocks are targeted, but according to determination 605, blocks other than 507 are not targeted for simulation model creation, and the process moves to process 610, where the management information table 503 is updated. On the other hand, regarding 507, the simulation model 504 is
is created, and based on determination 607, the management information table is updated in process 609.

In both of the above two flows, a connection information table 405 or 505 is created in process 611, and a new simulation model is created.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the number of times that a simulation model of a logical block is created, and to reconstruct a simulation model of a logical block without any omission using the management information table and the connection information table. Hair can be shortened.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of creating a simulation model from circuit data, Figure 2 is a diagram showing the hierarchical structure of the target logic circuit, Figure 3 is a diagram showing simulation modeling of the circuit in Figure 2, and Figure 4 is a diagram showing an example of creating a simulation model from circuit data. The figure shows an overview of the procedure for creating a new simulation model from all circuit data, Figure 5 shows an overview of the procedure for creating a simulation model by reusing the simulation model before the change, and Figure 6 shows the outline of the procedure for creating a simulation model. It is a flowchart. 406...Simulation model before change. 506.507...Circuit data after change. 608-610... Creation of management information table. Atsushi Tsutomu 2 Figure 20/~206 Upper layer 207~2/θ 11! -Yo #i Ronoa zn-22
o E road and "7 (+'ftt201-2101-tft=)"

Claims (1)

[Claims] In a logic simulation method in which a simulation model equivalent to the logic circuit to be simulated is created on a computer and specific signal values are input to the model to simulate circuit operation, if a part of the logic circuit to be simulated is changed. , the simulation model created from the circuit data of the logic block including the part where the change exists and the simulation model of the logic blocks of other parts are newly created based on the management information of the simulation model and the connection information between the logic blocks. A logical simulation model creation method characterized by creating a simulation model.