JPH03248469A - Mos type semiconductor device - Google Patents
Mos type semiconductor deviceInfo
- Publication number
- JPH03248469A JPH03248469A JP2046099A JP4609990A JPH03248469A JP H03248469 A JPH03248469 A JP H03248469A JP 2046099 A JP2046099 A JP 2046099A JP 4609990 A JP4609990 A JP 4609990A JP H03248469 A JPH03248469 A JP H03248469A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- gate
- melting point
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- 238000002844 melting Methods 0.000 claims abstract description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052796 boron Inorganic materials 0.000 abstract description 2
- -1 boron ions Chemical class 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000011109 contamination Methods 0.000 abstract 1
- 239000003870 refractory metal Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、ＭＯＳ型半導体装置に関し、特に高融点金属
又は高融点金属のシリサイドからなるゲート電極を有す
るものに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a MOS type semiconductor device, and particularly to one having a gate electrode made of a refractory metal or a silicide of a refractory metal.
［従来の技術］
ＭＯＳ型半導体装置のゲート電極はポリシリコン電極が
主流であるが、そのシート抵抗が高いので、ＶＬＳＩの
ように素子が微細化しチップサイズが大きくなるにつれ
、その配線容量による遅延時間が問題になり、高融点金
属または高融点金属シリサイドのゲート電極および配線
を用いる。このとき、従来、ゲート電極はゲート絶縁膜
上に直接形成されていた。[Prior art] Polysilicon electrodes are the mainstream for the gate electrodes of MOS semiconductor devices, but because of their high sheet resistance, as elements become finer and the chip size increases, as in VLSI, the delay time due to the wiring capacitance increases. is a problem, and gate electrodes and wiring made of high-melting point metal or high-melting point metal silicide are used. At this time, conventionally, the gate electrode was formed directly on the gate insulating film.
〔発明が解決しようとする課題１
上記のＭＯＳ型半導体装置では、スパッタ法により直接
ゲート絶縁膜に電極膜を被着してゲート電極を形成する
ので、ゲート絶縁膜との間は不安定であり、ゲート電極
からの不純物イオンが絶縁膜に入り、トランジスタ特性
が変動するという欠点がある。また、熱処理工程で、ゲ
ート絶縁膜との反応が生じないようにゲート電極材料の
選択に制約が生ずる欠点がある。[Problem to be Solved by the Invention 1] In the above MOS semiconductor device, since the gate electrode is formed by depositing the electrode film directly on the gate insulating film by sputtering, the relationship between the electrode film and the gate insulating film is unstable. However, impurity ions from the gate electrode enter the insulating film, resulting in fluctuations in transistor characteristics. Another disadvantage is that there are restrictions on the selection of gate electrode materials in order to prevent reactions with the gate insulating film during the heat treatment process.
本発明の目的は、上記の欠点を除去し、低抵抗の高融点
金属または高融点金属シリサイドのゲート電極で、安定
な特性を有するＭＯＳ型半導体装置を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a MOS type semiconductor device having stable characteristics using a gate electrode made of a low-resistance refractory metal or refractory metal silicide.
［課題を解決するための手段］
本発明のＭＯＳ型半導体装置は、ゲート絶縁膜とゲート
電極となる高融点金属または高融点金属のシリサイドと
の間にバリアメタル層を設けたもので、バリアメタル層
としてはＴｉＮ層またはＴｉＷ層が用いられる。本発明
の高融点金属または高融点金属のシリサイドからなるゲ
ート電極を有するＭＯＳ型半導体装置は、ゲート絶縁膜
と前記ゲート電極との間にバリアメタル膜を設けるよう
にしたもので、バリアメタル膜の材質はＴｉＮまたはＴ
ｉＷとしている。[Means for Solving the Problems] The MOS semiconductor device of the present invention has a barrier metal layer provided between a gate insulating film and a high melting point metal or a silicide of a high melting point metal serving as a gate electrode. A TiN layer or a TiW layer is used as the layer. A MOS type semiconductor device having a gate electrode made of a refractory metal or a silicide of a refractory metal according to the present invention is such that a barrier metal film is provided between a gate insulating film and the gate electrode. Material is TiN or T
It is called iW.
〔作 用 １
バリアメタル膜は、材質上極めて安定で、ゲート酸化膜
およびゲート電極の高融点金属または高融点金属シリサ
イドと反応せず、したがってゲート絶縁膜は汚染されず
トランジスタ特性の変動がなくなる。また耐熱性を向上
させる。[Function 1] The barrier metal film is extremely stable in terms of material and does not react with the high melting point metal or high melting point metal silicide of the gate oxide film and the gate electrode, so the gate insulating film is not contaminated and the transistor characteristics do not fluctuate. It also improves heat resistance.
〔実施例］
以下、本発明の一実施例について図面を参照して説明す
る。第１図は実施例の製造工程を示す縦断面図である。[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a longitudinal sectional view showing the manufacturing process of the embodiment.
この例は、ゲート電極にＷシリサイドを用いたｐ型ＭＯ
Ｓトランジスタの場合である。第１図ｆａｌ に示すよ
うにｎ型シリコン基板１０１にフィールド酸化膜１０２
を形成した後、熱酸化法を用いてゲート酸化膜１０３を
形成する０次に全面にＴｉのリアクティブスパッタ法に
より、１０００人程度のＴｉＮ膜１０４のスパッタを行
なう。次に全面にゲート電極となるＷシリサイドｆｆｌ
１０５を例えば１０００〜２０００１程度堆積する。This example is a p-type MO using W silicide for the gate electrode.
This is the case of an S transistor. As shown in FIG. 1, a field oxide film 102 is formed on an n-type silicon substrate 101.
After forming a gate oxide film 103 using a thermal oxidation method, a TiN film 104 is sputtered by about 1000 layers on the entire surface of the first order by a reactive sputtering method of Ti. Next, the W silicide ffl becomes the gate electrode on the entire surface.
105, for example, about 1000 to 20001.
そしてレジストを全面に塗布した後、パタニングしたレ
ジスト１０６をマスクとして、第１図ｔｂｌ に示すよ
うに反応性イオンエツチングを行ない、ゲート電極を形
成する。この状態でゲート電極１０５′はその下にバリ
アメタル膜１０４′を介してゲート酸化膜１０３′ と
接する。After applying a resist to the entire surface, using the patterned resist 106 as a mask, reactive ion etching is performed as shown in FIG. 1 tbl to form a gate electrode. In this state, the gate electrode 105' is in contact with the gate oxide film 103' via the barrier metal film 104' underneath.
次に第１図（ｃｌ に示すように全面に高濃度、例えば
注入量１０”〜ｌＯＩ６１０ｌ６程度のボロンイオンの
注入を行ない、ｐ＋拡散層領域１０７を形成し、つづい
て層間絶縁膜１０８を形成し、アルミニウム配線１０９
を設ければ、バリアメタル膜としてのＴｉＮ膜を有する
Ｗシリサイドゲートからなるｐ型ＭＯＳｌ−ランジスタ
を形成することができる。Next, as shown in FIG. 1 (cl), boron ions are implanted at a high concentration over the entire surface, for example, at an implantation amount of about 10'' to 1OI61016 to form a p+ diffusion layer region 107, and then an interlayer insulating film 108 is formed. , aluminum wiring 109
By providing , it is possible to form a p-type MOS l-transistor consisting of a W silicide gate having a TiN film as a barrier metal film.
〔発明の効果］
以上説明したように本発明は、ゲート絶縁膜と高融点金
属又は高融点金属のシワサイドからなるゲート電極との
間にバリアメタル膜をはさむことにより、ゲート電極か
らの不純物イオンの拡散によるトランジスタのＶア（ス
レシホールド電圧）の変動が従来０．２Ｖ程度あったも
のに対し、０．１Ｖ程度におさえることができる。さら
に、ゲート酸化膜との反応に対する耐熱性を向上させ、
ゲートの歩留りを７０％から９０％程度に改善すること
ができる。また、信頼性も向上する。さらに、耐熱性の
向上は、ゲート電極材料の選択の巾を広げ、ポリシリコ
ンゲートプロセスとの整合性をよくする効果がある。[Effects of the Invention] As explained above, the present invention suppresses impurity ions from the gate electrode by sandwiching a barrier metal film between the gate insulating film and the gate electrode made of a high melting point metal or a wrinkled side of a high melting point metal. The variation in Va (threshold voltage) of the transistor due to diffusion, which conventionally was about 0.2V, can be suppressed to about 0.1V. Furthermore, it improves heat resistance against reactions with the gate oxide film,
The gate yield can be improved from about 70% to about 90%. Also, reliability is improved. Furthermore, improved heat resistance has the effect of widening the selection range of gate electrode materials and improving compatibility with polysilicon gate processes.
第１図は本発明の一実施例を製造する工程の縦断面図で
ある。
ｌロト・−ｎ型シリコン基板、
１０３、１０３’・・・ゲート酸化膜、１０４・・・
ＴｉＮ膜、
■０４′ ・・・バリアメタル膜、
１０５−・−Ｗシリサイド膜、
１０５’ ・・・ゲート電極、
１０７・・−ｐ十数散層領域、
１０８・・・層間絶縁膜、
１０９・・−アルミニウム配線。
特
許
出
願
人
日本電気株式会社FIG. 1 is a longitudinal cross-sectional view of a process for manufacturing an embodiment of the present invention. lroto-n type silicon substrate, 103, 103'... gate oxide film, 104...
TiN film, ■04'...Barrier metal film, 105--W silicide film, 105'...Gate electrode, 107...-P dozen-odd scattered layer region, 108...Interlayer insulating film, 109-・-Aluminum wiring. Patent applicant NEC Corporation
Claims (1)
イドからなるＭＯＳ型半導体装置において、ゲート絶縁
膜と前記ゲート電極との間にバリアメタル膜を設けたこ
とを特徴とするＭＯＳ型半導体装置。 ２、前記バリアメタル膜の材質が、ＴｉＮまたはＴｉＷ
である特許請求の範囲の請求項１記載のＭＯＳ型半導体
装置。[Claims] 1. A MOS type semiconductor device in which the gate electrode is made of a high melting point metal or a silicide of a high melting point metal, characterized in that a barrier metal film is provided between the gate insulating film and the gate electrode. MOS type semiconductor device. 2. The material of the barrier metal film is TiN or TiW.
A MOS type semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2046099A JPH03248469A (en) | 1990-02-26 | 1990-02-26 | Mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2046099A JPH03248469A (en) | 1990-02-26 | 1990-02-26 | Mos type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03248469A true JPH03248469A (en) | 1991-11-06 |
Family
ID=12737548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2046099A Pending JPH03248469A (en) | 1990-02-26 | 1990-02-26 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03248469A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| JP2011181893A (en) * | 2009-12-10 | 2011-09-15 | Internatl Rectifier Corp | Group iii nitride transistor including highly-conductive source/drain contact, and method of manufacturing the same |
-
1990
- 1990-02-26 JP JP2046099A patent/JPH03248469A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6790749B2 (en) | 1992-10-09 | 2004-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US7109108B2 (en) | 1992-10-09 | 2006-09-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device having metal silicide |
| US7602020B2 (en) | 1992-10-09 | 2009-10-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7723788B2 (en) | 1992-10-09 | 2010-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US8017506B2 (en) | 1992-10-09 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| JP2011181893A (en) * | 2009-12-10 | 2011-09-15 | Internatl Rectifier Corp | Group iii nitride transistor including highly-conductive source/drain contact, and method of manufacturing the same |
| US9378965B2 (en) | 2009-12-10 | 2016-06-28 | Infineon Technologies Americas Corp. | Highly conductive source/drain contacts in III-nitride transistors |
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