JPH03242781A - Ic card system - Google Patents

Abstract

PURPOSE:To improve communication efficiency between a reader/writer and an IC card by continuously transmitting data from a memory to the reader/ writer even when a reading command is not received at the time of applying an identification(ID) code to the data, and when the reader/writer detects the ID code, continuously receiving the transmitted data. CONSTITUTION:A code applying means 35 can apply an ID code to a reading response. Even when a reading command is not received from the reader/writer 32a transmitting means 34 in the IC card 31 continuously transmits data from the memory 36 to the reader/writer 32. On the other hand, the reader/writer 32 continuously receives the data transmitted from the means 34 by a receiving means 33 at the time of detecting the ID code. Thus, the efficiency of data reading from the IC card can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an IC card system that controls data communication between a reader/writer and an IC card.

<Prior Art> Conventionally, this type of IC card system has been configured with a reader/writer, an IC card, and the like.

These reader/writers and IC cards have a well-known configuration, and include a CPU5, RAM5, ROM, and EEPROM.
, interface, etc. Data is exchanged between the reader/writer and the IC card via this interface. In this case, this data is generally sent in messages of arbitrary length.

When this message is long, it is divided into blocks of a certain size for transmission reasons.
Or what is received.

The data communication procedure between the IC card and the reader/writer will be explained below.

FIG. 12 is a sequence diagram showing the data communication order in the conventional IC cart system.

FIG. 13 is a diagram for explaining a transfer method when data stored in a memory is transferred to a communication buffer in a conventional IC card.

In FIG. 12, 11 is a read command sent from the reader/writer, and 12 is a read response sent from the IC card.

The read command 11 is a command signal used when the reader/writer requests data from the IC card. The read response 12 is a response signal to the reader/writer in response to reading data.

On the other hand, as shown in FIG. 13, in the IC card, 13 is a RAM shown in the memory map, and 14 is an EEPROM also shown in the memory map.

This RAM 13 has an area for temporarily storing data to be transmitted to the reader/writer, that is, a communication buffer 15. Therefore, the capacity of the communication buffer 15 defines the block size for data communication between the IC card and the reader/writer.

On the other hand, the EEPROM 4 holds read data to be sent to the reader/writer.

Here, with reference to FIG. 13, the procedure when the CPU of the IC card transmits data of a size longer than the communication buffer 15 to the reader/writer will be described.

The CPU of the IC card divides the data held in the EEPROM (memory) 14 into a plurality of data blocks 16 so as to have the above-mentioned block size Lb, and then stores the divided data in the memory 14 using this block 16 as a unit. from there to the communication buffer 15 in the RAM 13.

Next, the CPU of the IC card, as shown in FIG.
When a read command 11 is received from the reader/writer, data is set in the communication buffer 15 from the EEPROM 14, and then the data in the communication buffer 15 is transmitted to the reader/writer along with the read response 12. In this case, the CPU of the IC card sends a start byte 17, a length byte 20a, and a control byte 2ob, each of which is one byte indicating the start of data, as a read response, and then sequentially sends the data 18 in the communication buffer 15 one byte at a time. do.

When all the data (Lb worth) in the communication buffer 15 has been transmitted, the CPU of the IC card transmits a 1-byte check code byte 19 for checking the data of that block.

Next, if the read command 11 from the reader/writer is further received, the CPU of the IC card transfers the second block data Lb16 from the EEPROM 14 to the RA.
It is transferred to the communication buffer 15 of M13. Thereafter, block data Lb16 is sequentially transmitted using the above transmission procedure.

Note that if continuous block data 16 exists, data (chain code) indicating that the block data 16 exists is transmitted under the control of the CPU (control pie).
20b (see Figure 13). Therefore, while receiving this chain code, the reader/writer repeatedly reads the block data 16 by repeatedly transmitting the read command 11 to the IC card.

The IC card also receives data 18 from the communication buffer 15.
When sending 1 byte at a time, it was sent sequentially within the character waiting time. The character waiting time is a fixed waiting time, for example, 100 m5, after the reader/writer receives 1 byte of data 18.

If the reader/writer cannot receive the next 1 byte of data 18 within this character waiting time, the reader/writer's CPU sends an error message to the IC card and forcibly ends the data communication.

<Problem to be Solved by the Invention> However, in such a conventional IC card system, between the reader/writer and the IC card, a block unit of a fixed size defined by the capacity of the communication buffer 15 of the IC card, for example, is transmitted between the reader/writer and the IC card. Data is exchanged.

Therefore, when the IC card sends data with a size longer than the communication buffer 15 to the reader/writer, it divides this data into this block size, waits for the read command 11 from the reader/writer, and then sends the data in this divided unit together with the read response 12. Lb data 16 was being sent to the reader/writer.

Therefore, when the amount of communication data transmitted from the IC or card is large, that is, when the number of transmission blocks is large, the number of times the read command 11 and read response 12 are communicated between the reader/writer and the IC card is large. It has become. This has led to a decrease in communication efficiency between the reader/writer and the IC card.

That is, the IC card cannot send data exceeding the capacity of its communication buffer 15 to the reader/writer in one response. Therefore, when reading data from an IC card having a communication buffer with a small capacity, there is a problem that the efficiency of data reading is low.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an IC card system that can improve the efficiency of reading data from an I/C card.

<Means for Solving the Problems> As shown in FIG. 1, the present invention allows an IC card 31 to read data held in its memory 36 along with a read response in response to a read command from a reader/writer 32. , the reader/writer 32. At the same time, if the reader/writer 32 receives this read response within a predetermined time, it sends the next read command to the IC card 31 to read the desired length from the memory 36 of the IC card 31. In an IC card system capable of reading data, the IC card 31 includes a code attaching means 3δ for attaching an identification code to the read response, and when the identification code is attached to the memory, even when the read command is not received. 36, to the reader/writer 32, and when the reader/writer 32 detects the identification code, the reader/writer 32 continuously transmits the data transmitted from the transmitting means 34. This is an IC card system equipped with a receiving means 33 for receiving information.

<Operation> In the present invention, the code adding means 35 can add an identification code to the read response.

In this case, even when not receiving a read command from the reader/writer 32, the transmitting means 34 of the IC card 31 continuously transmits data from the memory 36 to the reader/writer 32. On the other hand, when the reader/writer 32 detects this identification code, the receiving means 33 successively receives four transmission data from the transmitting means 34.

<Example> Hereinafter, an example of an IC card system according to the present invention will be described with reference to the drawings.

2 to 10 show a first embodiment of the present invention.

2 is a block diagram showing a schematic hardware configuration of an IC card system according to a first embodiment of the present invention.

In the same figure, 41! , t: IC card,
42 is a reader/writer.

The IC card 41 is a CP that controls the human output of data.
U43, RAM44 having a communication buffer, PROM45 storing a predetermined processing procedure program, and RAM
44 communication buffers (e.g., 512
~16 bytes) and stores communication data.
It is composed of a ROM (memory) 46 and an interface 47 that controls the exchange of communication data.

The communication buffer is an area of the RAM 44 that temporarily stores data to be sent to the reader/writer 42. Therefore, depending on the capacity of this communication buffer, the IC card 4
The block size (for example, 64 bytes) for data communication between the reader/writer 1 and the reader/writer 42 is defined.

On the other hand, the reader/writer 42 has a well-known configuration, and has a CP
This interface 4 consists of U, RAM (communication buffer), ROM, power supply, interface 47, etc.
Data is exchanged with the IC card 41 via the IC card 7.

The data communication procedure between the IC card 41 and the reader/writer 42 will be explained below.

FIG. 3 is a sequence diagram showing the order of data communication in the IC card system according to the first embodiment of the present invention.

FIG. 4 is a diagram for explaining a transfer method when data stored in the memory 46 is transferred to the communication buffer in the IC card according to the first embodiment of the present invention.

In these figures, 51 is the IC from the reader/writer 42.
A read command sent to the card 41, 52
is a read response transmitted from the IC card 41 to the reader/writer 42.

The read command 51 is an instruction code used when the reader/writer 42 requests data from the IC card 41.

On the other hand, the read response 52 refers to the reader/writer 42
This is the response code when responding to a data read request. This read response 52 includes divided data 53.
is added.

This divided data 53 is data stored in the memory 46 and divided into the block size units (64 bytes).

Therefore, as shown in FIG. 3, the IC card 41 is
When receiving the read command δ1 from the reader/writer 42, the divided data 53 is added to the read response 52 and transmitted to the interface 47 of the reader/writer 42.

Here, if the capacity of the data to be transmitted is larger than the capacity (64 bytes) specified by the communication buffer, an identification code is written in the area 60a of the read response 52 that normally stores the length of the data. Il'OOJ
Grant.

On the other hand, the reader/writer 42 continuously receives the transmission data from the IC card 41 by detecting this identification code. That is, even when the reader/writer 42 receives data from the IC card 41, the reader/writer 42 maintains the receiving state and does not issue a reception error signal or transmit the read command 51.

Note that the reader/writer 42 ends receiving data when the data from the IC card 41 is not transmitted during the character waiting time CWT.

Further, in the IC card 41, this read command 51
The divided data is sequentially transmitted one byte at a time to the reader/writer 42 without waiting for the reception of the data (see FIG. 4).

Here, the transfer of data from the memory 46 to the communication buffer will be explained with reference to FIG.

Upon receiving the read command 51, the IC card 41 transfers data corresponding to the capacity of the communication buffer from the EEPROM 4B to the communication buffer of the RAM 44. Then, the IC card 41 transmits the data from this communication buffer together with the read response 52 one byte at a time to the reader/writer 42 as described above. After all the data in the communication buffer is transmitted, for example, 1 byte of data Ls is transferred from the EEPROM 46 to the communication buffer and transmitted to the reader/writer 42 within the character waiting time CWT.

When outputting the data in this communication buffer, after all the data in the communication buffer is output, the following data is read from the EEPROM 46 to the communication buffer. Note that Ls indicates the data capacity that can be transmitted within this character waiting time (100 ms), and it may be possible to transfer multiple bytes of data.

A program executed by the IC card system having the above configuration will be explained based on the flowcharts shown in FIGS. 5 to 10.

FIG. 5 is a flowchart showing the reading procedure in the IC card 41 according to the first embodiment of the present invention.

When the IC card 41 is inserted into the reader/writer 42,
A power supply and a clock signal are supplied to the IC card 41, and a reset command is sent to initialize the IC card 41 (step Sl).

The initialized IC card 41 transmits an ATR signal containing information such as the block size defined by the communication buffer to the reader/writer 42 (step S2). I
The C card 41 enters a command reception waiting state.

Here, the reader/writer 42 that has received the ATR signal transmits a read command to the IC card 41.

Therefore, when the IC card 41 receives the read command (step S3), it manually enters data into the following variables (registers).

The capacity of the communication buffer of the reader/writer 42 is determined in the RTU (step S4), the capacity of the communication buffer of the IC card 41 is determined in the ITU (step S5), and the data capacity to be transmitted to the SDA is determined manually (step S6). be. Here, the data on the capacity of the communication buffer of the reader/writer 42 is stored in the read command. Note that RTU, ITU, and SDA can also be omitted.

Next, from the variable SDA indicating the amount of data to be transmitted to IC
Subtract the capacity jII TU of the communication buffer of the card 41,
The result is stored in the variable SIS (step S7).

Here, to judge the sign of this SIS, step S8),
If the data volume jiSDA to be transmitted is smaller than or equal to the communication buffer capacity ITU of the IC card 41 (SI S2O), step S9 (transmission processing 1 subroutine) is executed.

On the other hand, the data capacity SDA to be transmitted is
If the communication buffer capacity of ff1ITU is larger than (S
I S > 0), read out the identification code "OO" and store it in the length byte of the response.Step S10)
, sends a read response to the reader/writer 42 (
Step 5ll).

Next, from the data amount SDA to be transmitted, the reader/writer 4
The capacity RTU of communication buffer No. 2 is subtracted, and the calculation result is stored in variable SR3 (step 512).

Now, let's judge the sign of this SR5 (step 513).
, if the data capacity SDA to be transmitted is smaller than or equal to the communication buffer capacity l1RTU of the reader/writer 42 (SR5≦0), step 514 (transmission processing 2
subroutine).

On the other hand, the data capacity SDA to be transmitted is
If it is larger than the communication buffer capacity RTU of No. 2,
3) 0), the transmission processing 3 subroutine is executed (step 515).

When one of the transmission processing subroutines is completed, it is determined whether or not to repeatedly execute the read main routine (step 816). If the read main routine is to be repeatedly executed, the process is executed again from step S3.

On the other hand, if the read main routine is not repeatedly executed, it ends.

As described above, one of the transmission processing subroutines is executed depending on the amount of data to be transmitted to the reader/writer 42.

The transmission processing 1 subroutine will be explained. This is the case when the amount of data to be transmitted is less than the communication buffer capacity of the IC card 41.

FIG. 6 is a flowchart showing the transmission processing subroutine according to the first embodiment of the present invention.

First, the IC card 41 transmits a start byte to the reader/writer 42 (step 521), and then transmits a length byte indicating the length of the data and a control byte indicating that the data is not chained (steps 522 to 42).
523). Next, 1 byte of data is transferred to the reader/writer 42.
(step 524). In this case, it is assumed that the communication buffer of the IC card 41 stores data equal to or less than this capacity corresponding to its capacity.

Next, subtract 1 from the data amount SDA to be sent (
Step 525), it is determined whether there is any data left to be transmitted (whether 5DA=O in step 526).

If there is data left to send (SDA≠0),
The process is repeated from step S24.

On the other hand, if there is no data left to send (SDA=
0) sends a check code byte to the reader/writer 42 (step 527), and returns to the main routine.

Next, the transmission processing 2 subroutine will be explained. This is a case where the amount of data to be transmitted is larger than the communication buffer capacity of the IC card 41 but less than the communication buffer capacity of the reader/writer 42.

FIG. 7 is a flowchart showing the transmission processing 2 subroutine according to the first embodiment of the present invention.

First, a start byte is transmitted (step 531), followed by a length byte containing an identification code and a control byte indicating chaining (step S32,
33). Next, 1 byte of data is transmitted to the reader/writer 42 (step 534). In this case, IC card 4
It is assumed that one communication buffer stores data of a capacity corresponding to its capacity.

Next, 1 is subtracted from the data amount SDA to be transmitted, and the subtraction result is stored again in the variable register SDA indicating the data amount to be transmitted (step 535).

Then, it is determined whether or not this SDA is positive as a result of the subtraction (step 536). If it is positive (SDA>0), it is then determined whether all the data in the communication buffer has been transmitted to the reader/writer. (Step 537). If there is data that has not been transmitted yet, the process returns to step S34. If all data has been transmitted, transfer Ls worth of data from the memory 46 to the communication buffer (step 338);
Step S34 is executed again. This step S38
is executed within the character waiting time of 100m5.

On the other hand, if there is no data left to send (SDA
≦0), the check code byte is sent to the reader/writer 42 (step 539), and the process returns to the main routine.

Next, the transmission processing 3 subroutine will be explained. In this case, the data to be transmitted exceeds the communication buffer capacity (indicated by RTU) of the reader/writer 42.

FIG. 8 is a flowchart showing the transmission processing 3 subroutine according to the first embodiment of the present invention.

First, a start byte is transmitted to the reader/writer 42 (step 541), followed by a length byte containing an identification code and a control byte indicating that the data is chained (steps S42, 43).

Next, 1 byte of data is transmitted to the reader/writer 42 within a predetermined time (100 ms) (step 544). In this case, it is assumed that the communication buffer of the IC card 41 stores data of a capacity corresponding to its capacity.

Next, 1 is subtracted from the variable SDA indicating the amount of data to be transmitted, and the result of this subtraction is stored again in the variable SDA (step 545). Then, based on the subtraction result, it is determined whether there is any data left to be transmitted (step 546).
).

Then, if there is no data left to send (S
DA≦O), execute step S51 and transmit the check code byte to the reader/writer 42.

On the other hand, if there is still data to be sent (SDA
>O), communication buffer capacity of reader/writer 42 ff1R
Subtract 1 from TU and store the result of this subtraction in register RTU.
(step 547).

Then, it is determined whether this RTU is correct or not in step 54.
8) If positive (RTU>O), there is free space in the communication buffer of the reader/writer 42, so step S49. The process returns to S44 via S50 to transmit the data. Then, in step S49, it is determined whether all the data in the communication buffer has been transmitted to the reader/writer 42. If there is any data that has not been transmitted yet, the process returns to step S44, and if all data has been transmitted, Ls worth of data is transferred from the memory 46 to the communication buffer (step 550).

On the other hand, if there is no free space in the communication buffer of the reader/writer 42 (RTU≦O), a check code byte is sent to the reader/writer 42 (step 551), and the process returns to the main routine.

Next, the main routine of data reception processing in the reader/writer 42 will be explained.

FIG. 9 is a flowchart showing the reception processing main routine according to the first embodiment of the present invention.

First, the reader/writer 42 receives the start byte located at the head of the read response 52 from the IC card 41 (step 561), and then determines whether or not the identification code "OO" has been transmitted (step 562). .

When the identification code is detected (YES in S62), the interrupt destination to be executed when no data is transmitted after the character waiting time CWT is set in the process of step S65 (step 563). Next, a 1-byte reception subroutine is executed (step 564).

During the execution of the l-byte reception subroutine, when the character ζ lid waiting time is exceeded, the data stored in the communication buffer of the reader/writer 42 is transferred and stored, for example, in its memory (step 565), and the process ends.

If the identification code has not been received in step S62, the length of the data has been set, so
This length is set in the counter Lp (step 566).

Then, the start address of a "time-over error program" to be executed when the character waiting time CWT is exceeded is set as the interrupt destination address. As a result, the reader/writer 42 receives 1 byte of data, and if it cannot receive the next 1 byte of data within the character waiting time CWT, it executes a "time-over error program" (step 567).

Next, the counter Lp is decremented by 1 (step 568). Then, data is received one byte at a time (
Step 569) Subroutine processing is performed.

Then, the subroutine is repeated until the counter Lp counts up (step 570), and after waiting for data of a desired length to be stored in the communication buffer, the data is transferred to the memory (step 571). Then exit this program.

Next, the 1-byte reception subroutine will be explained.

FIG. 10 is a flowchart showing a 1-byte data reception subroutine of the reader/writer according to the first embodiment.

First, when the reader/writer 42 receives 1 byte of data transmitted from the IC card 41 (step 581)
, the value obtained by adding CWT to the value of the free running counter FRC is assigned to OCR (conveyor register for oc i interrupt) (step 582). This is to check whether 1 byte of data has been received within the character waiting time. Next, oci is enabled, and an interrupt signal that is not received within the character waiting time is accepted (step 583).

Therefore, in the IC card system according to the first embodiment of the present invention, a plurality of pieces of divided data 53 can be transmitted in one read response 52.

Furthermore, data exceeding the capacity of the communication buffer of the IC card 41 can be transmitted. In other words, reader/writer 4
Even if the communication buffer size of the IC card 2 and the communication buffer size of the IC card 41 are different, the IC card 4 can transmit data according to the capacity of the communication buffer of the reader/writer 42.

Further, FIG. 11 is a block diagram showing a second embodiment of the present invention.

As shown in this figure, the IC card used in the IC card system has the following configuration.

That is, this IC card 21 has a transmission means 24, a memory 26, a communication buffer 27, and a transfer means 28.

The transmitting means 24 is, for example, the reader/writer 4 as described above.
When receiving a read command from the reader/writer 2, the data held in the communication buffer 27 is sent to the communication buffer of the reader/writer 42.

The memory 26 holds data, and is composed of, for example, an EEPROM or the like having a predetermined memory capacity.

The communication buffer 27 temporarily stores the data transferred from the memory 26, and has a smaller capacity than the memory 26.

When the data size read from the memory 26 is larger than the memory capacity of the communication buffer 27, the transfer means 28 sequentially sets the data in the communication buffer 27 without receiving a read command from the reader/writer 42. .

Therefore, in the IC card 21 according to this embodiment, when a read command is received from the reader/writer 42, the transmitting means 24 transmits data from the communication buffer 27 one byte at a time to the reader/writer as in the above embodiment. 4
Send to 2.

Here, when all the data in the communication buffer 27 has been transmitted, the transfer means 28 sequentially sets the data from the memory 26 into the communication buffer 27 without receiving a read command from the reader/writer 42. For example, one byte to several bytes of data is transferred from the memory 26 to the communication buffer 27 during the character waiting time.

Therefore, the length of data transmitted to the reader/writer 42 is not restricted by the capacity of the communication buffer 27.

Furthermore, even if the communication buffer size of the IC car F'21 is smaller than the communication buffer size of the reader/writer 42, the data transmitted to the reader/writer 42 is not restricted by the communication buffer size of the IC card 21. In other words, this IC card 21 can transmit data of a size larger than its communication buffer size to the reader/writer 42. the result,
We were able to improve data transmission efficiency.

<Effects> As described above, according to the present invention, data larger than the block size of data communication can be transmitted by sending and receiving one command (read command and read response). As a result, it was possible to improve the communication efficiency between the reader/writer and the IC card.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an IC card system according to the present invention, FIG. 2 is a block diagram showing the hardware configuration of the IC card system according to the first embodiment of the present invention, and FIG. FIG. 4 is a sequence diagram showing the data communication order in the IC card system according to the first embodiment of the present invention. 1. In the C card according to the first embodiment of the present invention, data stored in the memory is transferred to the communication buffer FIG. 5 is a diagram for explaining the time transfer method.
A flowchart showing the reading procedure in the IC card according to the embodiment, FIG. 6 is a flowchart showing the transmission processing 1 subroutine according to the first embodiment of the present invention, and FIG. 7 is a flowchart showing the transmission processing according to the first embodiment of the present invention. FIG. 8 is a flowchart showing the transmission processing 3 subroutine according to the first embodiment of the present invention; FIG. 9 is a flowchart showing the reception processing main routine of the reader/writer according to the first embodiment of the present invention; FIG. 10 shows the first embodiment of the present invention.
A flowchart showing a 1-byte data reception subroutine of a reader/writer according to an embodiment, FIG. 11 is a block diagram showing the configuration of an IC card according to a second embodiment of the present invention, and FIG. 12 shows data in a conventional IC card system. FIG. 13, a sequence diagram showing the communication order, is a diagram for explaining a transfer method when data stored in a memory of a conventional IC card is transferred to a communication buffer. 35 ・ 36 ・

Claims (1)

[Claims] In response to a read command from a reader/writer, the IC
The card sends the data held in its memory along with the read response to the reader/writer in blocks of a certain size, and if the reader/writer receives this read response within a predetermined time, it issues the next read command. In an IC card system that can read data of a desired length from the memory of the IC card by transmitting it to the IC card,
The card includes a code assigning means for assigning an identification code to the read response, and a transmitting means for continuously transmitting data from the memory to the reader/writer even if the read command is not received when the identification code is assigned. , and when the reader/writer detects the identification code,
An IC card system comprising: receiving means for continuously receiving transmission data from the transmitting means.