JPH03232200A - Mos semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent a current consumption from being increased due to a defective part by detecting an address of a normal memory cell array having a defective part with an output of an replaced address program circuit during the precharge period and stopping the delivery of a precharge control signal to a precharge circuit of the normal memory cell array corresponding to the detected replacement address so as to stop the precharge of a digit line. CONSTITUTION:A replacement address detection control circuit 7 is provided with plural logic circuits 71 and a Y decode circuit 2 generates a control signal PHIC turning off a transistor (TR) Q1 of a normal memory cell array of a memory cell array section 1 corresponding to a replacement address when a precharge control signal PHIp is an active level. That is, in the case of precharge when the precharge control signal PHIp is at a high level, the control signal PHIC goes to a low level and the TR Q1 of the normal memory cell array having a defective part is turned off, then digit lines DL1, inverse of DL1 of the memory cell array are not precharged. Thus, even when a word line WL is in short-circuit with a digit line, no current flows through the short-circuit point.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 type semiconductor memory device, and particularly to an MO8 type semiconductor memory device equipped with a redundant circuit.

[Conventional technology]

In the conventional MO8 type semiconductor memory device of this type, the redundancy circuit system is to replace a defective word line, defective digit line, or defective bit with a redundant word line or redundant digit line in units of word lines or digit lines. is common.

Here, a description will be given of a redundant circuit configuration particularly when a defective digit line is replaced with a redundant digit line.

FIG. 2 is a circuit diagram showing an example of a conventional MOa type semiconductor memory device.

The memory cell array section LA has one end connected to a sense amplifier 41.
A pair of input/output lines IOL and IO via the Y switch 51
Paired digits connected to L, IIDLI, DLI
, a plurality of word lines WL whose one end is connected to the word line reset circuit 6, and these word lines WL and digital lines D.
A plurality of memory cells MC connected to Ll and DLl, and a digit line DL.

A plurality of normal memory cell columns each having a precharge circuit 11 connected to DLl, and an input/output line IOL connected to one end via a redundant sense amplifier 4R and a Y switch 5B.
, a pair of redundant digit lines D connected to the IOL
LR9DLR1 A redundant memory cell equipped with a plurality of redundant memory cells MCR connected to this digital line DLR1 and a plurality of word lines WL, and a redundant precharge circuit connected to the digital line DLR9DLR. It is composed of columns.

The redundant decoder circuit 3 has fuses (Fl, F2゜-m
-) includes a replacement address program circuit 31A that sets the address to be replaced by disconnecting the Y address signal (Yl---) when a defect occurs in a normal memory cell column.
When the address of the defect is specified by The conversion inhibition signal AI is set to a low level and output.

The two Y decoder circuits include a decoding section 21 and a control section 22, and when a defective address is input and the Y switch and T activation inhibition signal AI becomes low level, the Y switch and T activation signal Y is activated.
SWl'ft inactivation level (low level) KL, when the Y address signal (Yt ---) specifies a normal (non-defective) address, the Y switch activation signal (Yswt) corresponding to that address is set to activation level and output.

The word line reset circuit 6 discharges the charge on the word line WL during precharging.

When a normal address is specified by the Y address signal (Yl---), the digit line DL1. of the normal memory cell column corresponding to this address is designated. DLl is Y sui,
When a defective address is specified, the Y switch 51 of the normal memory cell column is turned off and the redundant Y switch 51 is connected to the input/output lines IOL and IOL by the
R is turned on, and the digit lines DLR and DLR of the redundant memory cell column are connected to the input/output lines IOL and IOL.

, normal precharge circuit 1 of memory cell array section lA
1. The redundant precharge circuits ta operate simultaneously by the precharge control signal ΦP, and the memory cells MC and M
All digital and digital lines DL1°L)hl,L)LH,υ11 at a predetermined timing before reading data of eR, etc.
B f f9f Kan F) V Helk K 76゜ [Problems to be Solved by the Invention] The conventional MO8 type semiconductor memory device described above uses a normal precharge circuit 11. The redundant precharge circuit
, , DLR, DLR are precharged to a predetermined level, and the word line WL is discharged by the word line reset circuit 6 at the time of precharging, so that, for example, as shown in FIG. If a defect such as a short circuit (short circuit resistor r) occurs between the word line DLl and the word line WL and replacement is performed, the precharge circuit 11 is connected from the precharge potential supply point P to the digit line DL.

There is a drawback that current i flows in the path of → word line WL → word line reset circuit 6, increasing current consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide an MO8ffil semiconductor memory device that can prevent current consumption from increasing when a defect such as a short circuit between a digit line and a word line occurs.

[Means to solve the problem]

The MO8 type semiconductor memory device of the present invention includes corresponding first and second digit lines to which a plurality of memory cells are connected;
a precharge circuit that precharges the first and second digit lines to predetermined levels according to the transmitted precharge control signal; and a precharge circuit that is turned on and off according to the control signal and transmits the precharge control signal to the precharge circuit. A memory cell array section including a plurality of normal memory cell columns each equipped with a transistor and a redundant memory cell column, and when there is a defective part in the normal memory cell column of this memory cell array section, the memory cell of this defective part A replacement address program circuit is provided to set a column address, and when an external address signal specifies the address of the defective portion, the memory cell column in which the foal portion is located is replaced with the redundant memory cell column. a redundant decoder circuit that outputs a replacement signal for the precharge program; a replacement address detection control circuit that detects and outputs a replacement address set by the replacement address program circuit when the precharge control signal is at an active level; means for generating the control signal to turn off transistors in a normal memory cell column of the memory cell array portion corresponding to the replacement address output by the replacement address detection control circuit when the charge control signal is at an activation level. ing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The memory cell array section l includes first and second digit lines DL1 . . . corresponding to which a plurality of memory cells MC are connected.
DL1.) according to the precharge control signal ΦP transmitted via the transistor Qt. DL,
Precharge circuit 1 that precharges to a predetermined level
1. It also includes a plurality of normal memory cell rows and a redundant memory cell row (not shown) each provided in a transistor Q1 that is turned on and off by a control signal ΦC and transmits a precharge control signal ΦP to the precharge circuit 11. The conventional memory cell array section I shown in FIG.
The structure is such that a transistor Qt is added to A.

The redundant decoder circuit 3 includes a replacement address program circuit 31 that sets the address of the memory cell column of the defective portion when there is a defective portion in the normal memory cell column of the memory cell array section l, and receives a Y address signal (Yl) from the outside. ---
-) specifies the address of a defective part, it outputs a signal (A I, Y8WR) for replacing the memory cell column in which the defective part is located with the redundant memory cell column, and the replacement Each heater (
Ft.

The redundant decoder circuit 3 is similar to the conventional redundant decoder circuit 3 shown in FIG. 2, except that a signal for detecting a replacement address is taken out from one end of F2--).

The replacement address detection control circuit 7 includes a plurality of logic circuits 71, and when the precharge control signal ΦP is at an active level (high level) during precharging, the replacement address detection control circuit 7 detects the replacement set by the replacement address program circuit 31 using an active signal ΦM-o. Detects and outputs the address and precharge control signal Φ
When P is active at the inactivation level (low level), the active signal ΦA1 activates the external Y address signal (
Yl----) is output.

The Y decoding circuit 2 includes a decoding section 21 that inputs and decodes the output address signal of the replacement address detection control circuit 7, and a control section 22. It is similar to the conventional Y-lever 1 circuit 2A shown in FIG. 2, except that it has the function of generating a control signal ΦC that turns off the transistor Q1 of the normal memory cell column in the corresponding memory cell array section l. .

During precharging when the precharge control signal ΦP is at a high level, the output of the decoding section 21 of the Y decoder circuit 2 corresponding to the replacement address, that is, the control signal ΦC, becomes a low level, and the transistor Q of the normal memory cell column with the defective part is
Since digit line DLl and DL□ of this memory cell column are turned off, the digit lines DLl and DL□ are not precharged.

Therefore, for example, the word line WL and the digit lines DLl, D
Even if Ll is short-circuited, the current i as shown in FIG.
Since no current flows, it is possible to prevent current consumption from increasing.

Transistor Q in a normal memory cell section with no defective parts!
Since the output of the corresponding decoder 21, that is, the control signal ΦC, is at a high level, the digit line can be normally precharged.

〔Effect of the invention〕

As described above, the present invention detects the address of a normal memory cell column in which a defective part is present during the precharge period using the output of a replacement address program circuit, and then replaces the normal memory cell column corresponding to the detected replacement address. By stopping the transmission of the precharge control signal to the column precharge circuit and stopping the precharging of the digit line, even if the defective part is a short circuit between the digit line and the word line, the faulty part can be fixed. digits of a certain memory cell column.

Since the power line is not precharged, no current flows through the defective portion, and an increase in current consumption due to the defective portion can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional MO8 type semiconductor memory device, and FIG. 3 is a circuit diagram of an MOa type semiconductor memory device shown in FIG. FIG. 2 is a circuit diagram for explaining the problem. l, 1 person...Memory cell array section, 2, 2 degrees
°. Y decoder circuit, 3,3m... Redundant decoder circuit, 6... Word line reset circuit, 7...
...Replacement address detection control circuit, tt, tR...
・Precharge circuit, 21...decoding section, 2
2...Control unit, 31...Replacement address program circuit, 41.4 degrees. ...Sense amplifier, 51,5R... Y switch,
H, 71...Logic circuit, DLI, DLI, D
Ln, DLH...Digi, T line, Fl, F2.
...Hyuse, IOL. IOL... Input/output line, MC, MCH...
・Memory cell, Q,...transistor, WL・
...°°word line.

Claims (1)

[Claims] a pair of first and second digit lines to which a plurality of memory cells are connected; a precharge circuit that precharges the first and second digit lines to a predetermined level according to a transmitted precharge control signal; a memory cell array section including a plurality of normal memory cell columns each equipped with a transistor that is turned on and off by a control signal and transmits the precharge control signal to the precharge circuit; and a redundant memory cell column; A replacement address program circuit is provided for setting the address of the memory cell column of the defective portion when there is a defective portion in the normal memory cell column of the cell array section, and when an address signal from the outside specifies the address of the defective portion, the a redundancy decoder circuit that outputs a replacement signal for replacing a memory cell column with a defective portion with the redundant memory cell column; and a redundancy decoder circuit configured by the replacement address program circuit when the precharge control signal is at an active level. a replacement address detection control circuit that detects and outputs a replacement address that has been replaced; and a normal memory of the memory cell array portion corresponding to the replacement address that the replacement address detection control circuit outputs when the precharge control signal is at an active level. 1. A MOS type semiconductor memory device, comprising: means for generating the control signal for turning off transistors in a cell column.