JPH03231461A - Cell for gate array use and rom matrix for spread-type gate array use - Google Patents

Abstract

PURPOSE:To obtain a cell, for gate array use, which is suitable for constituting a ROM by a method wherein, in a cell for gate array use, 2<n> pieces of N-channel MOSFET's whose channel length and channel width are identical are arranged against one P-channel MOSFET. CONSTITUTION:A cell for gate array use contains two constituent units composed of a constituent unit in which four (n=2) N-channel MOSFET's are arranged in series against one P-channel MOSFET; adjacent diffusion layers are united; gates of the respective MOSFET's are separated. When a ROM is constituted of the cell, for gate array use, formed in this manner, the area occupied by the ROM can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to gate arrays, and in particular to ROM (read/read memory).
The present invention relates to a gate array cell suitable for configuring a gate array (only memory) and a ROM matrix configuration using the same.

[Conventional technology]

Conventionally, the structure of a gate array cell is either a structure in which the same number of pairs of P-channel MOSFETs and N-channel MOSFETs are used, as shown in FIG. It had a configuration with the addition of . In FIGS. 5 and 6, 400a.

400b is a gate array cell, 401 is an N-type well,
402 is a P type diffusion layer, 403 is an N type diffusion layer, and 404 is a polysilicon film. The circuit shown in FIG. 5 is suitable for logic circuits such as NAND circuits and NOR circuits, and the circuit shown in FIG. 6 is suitable for configuring cells of static RAM (random access memory).

[Problem to be solved by the invention]

However, in the gate array cell described above, since the number of MOSFETs included in one cell that can be expected to have the same characteristics is small, the number of ROM bits that can be configured with one cell is small, and when a ROM matrix is configured, the area is large. Therefore, it is not suitable for ROM. For example, in the cell of FIG. 5, an N-channel MOSFET,
Since only two P-channel MOSFETs are included each, no matter which MOSFET is used to construct a matrix, only a 1×2-bit matrix can be constructed per cell, and even in the cell of FIG. The maximum number of MOSFETs with the same characteristics included in a cell are the four N-channel MOSFETs provided in the upper stage of the cell.
ET is equivalent, but even if this is used, 2 × 2 per cell
There was a problem that only a matrix of bits could be configured, and that a large occupied area was required to introduce a ROM into the gate array. On the other hand, RO included in the gate array
In order to reduce the area occupied by M, a method has been put into practical use in which a part of the gate array cell is replaced with a ROM-dedicated cell in advance and the ROM is configured within that area. However, the size and individuality of the ROM that can be realized are limited by the number and arrangement of ROM-dedicated cells.

[Means to solve the problem]

The gate array cell of the present invention includes one P-channel MO
The ROM matrix for a gate array of the present invention includes a structural unit formed by arranging an SFET and 2' (n≧2) N-channel MOSFETs having the same channel length and the same channel width in a row in the vertical direction, and the ROM matrix for a gate array of the present invention A digit line made of a first layer metal film and a word line made of a second layer metal film are arranged on a base on which array cells are laid out in an array, and on the drain diffusion layer of the N-channel MOSFET in the gate array cell. The first contact hole provided through the contact hole
A ROM code is written depending on the presence or absence of a connection between a programming terminal made of a layered metal film and the digit line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a layout diagram showing an embodiment of the gate array cell of the present invention, and illustrates the case where n=2. FIG. 1(b) is a diagram in which the first layer metal film, second layer metal film, contact holes, and through holes necessary for constructing the ROM matrix are superimposed on FIG. 1(a). FIG. 1(c) shows an example of wiring when constructing a two-manpower NAND gate using the cell shown in FIG. 1(a).

In Fig. 1 (a>, (b), and (c)), 1°O is the cell outline, 101 is the N-type well, 102 is the P-type diffusion layer, and 10
3 is an N type diffusion layer, 104 is a polysilicon film, and 105 is an N type diffusion layer.
106 is a through hole that connects the polysilicon film and the first layer metal film; 107 is the first layer metal film; In particular, the ground line 1.7b is made of a first layer metal film, and 1.7b is a program terminal made of a first layer metal film provided through a contact hole 105 on the drain diffusion layer of the N-channel MOSFET. This is a digit line made of metal film. Furthermore, 108 is a word line made of a second layer metal film, 109 is a through hole between the first layer metal film and the second layer metal film, and 110 is a programming wiring made of the first layer metal film.

In Figure 1 (a), the gate array cell is one P
O8 between 4 N channels for channel MOSFET
It includes two structural units in which FETs are arranged in series, and has a configuration in which adjacent diffusion layers are connected, and the gates of each IVIO3 FET are separated. In Fig. 1(b), the wiring pattern for configuring the ROM matrix is superimposed on Fig. 1(a) as a base.
A word line 108 made of a second layer metal film running in the vertical direction is arranged for each of the two structural units, and a polysilicon film 104 that also serves as the gate electrode of the N-channel MOSFET belonging to each structural unit is connected to the word line 108 . , a through hole 109 between the first layer metal film and the second layer metal film, and the first layer metal film 107
and are connected via the contact hole 106 between the polysilicon film and the first layer metal film, and horizontally corresponding to each stage of the N-channel MOS FETs arranged in 2 x 4 stages within the cell. Four digit lines 107C of the first layer metal film are arranged in the direction, and each N-channel MOSF
On the N-type diffusion layer 103 on the drain side of the ET, there is a first layer connected to the train of the N-channel MOSFET through a contact hole 105 made of a diffusion layer and a first layer metal film.
A programming terminal 107b made of a layered metal film is provided. Also, N-channel MOSFE shared by each stage
The N-type diffusion layer 103 on the source side of T is connected to the ground line 107a made of the first layer metal film through a contact hole 105 between the diffusion layer and the first layer metal film, and is connected to the ground line 107a made of the first layer metal film. One cell constitutes a 2×4 bit ROM matrix. To write the ROM code, as shown in FIG. 1(b), the digit line 107c and the programming terminal 107b are connected using the programming wiring 110 (the shaded area in FIG. 1(b)) made of the first layer metal film. Depends on whether you do or not.

FIG. 1(c) is a diagram in which a wiring pattern for realizing a two-man NAND circuit is superimposed on the gate array cell of the embodiment of FIG. 1(a), and two P-channel MOSFETs are connected to each other.
A two-man power NAND circuit is constructed between the power supply line 107d and the ground line 107a using four of the eight N-channel MOSFETs. O8 between the lower two N channels in the cell
Since the FET is not used in this case, this area can be used as a wiring channel. Figure 1 (
As shown in the example c), there is no problem in realizing a normal logic gate circuit using the gate array cell of the present invention.

FIG. 2 is a diagram showing an example of a gate array cell whose cell size is smaller than that of FIG. 1 by sharing the gate electrode. This gate array cell uses a P-channel MOSFET and two upper stages of N-channel MOSFETs for the logic gate circuit, uses four lower stages of N-channel MOSFETs for the ROM matrix, and uses a static RAM cell (2 stages) for the ROM matrix. It can be realized without any problem by using all the MOSFETs for boats with human power output, and has the advantage that the occupied area is smaller than that shown in FIG. 1 (a>).

The gate array cell of the present invention has been described above using an example in which n=2, but to configure a ROM matrix, the minimum 4-bit output is usually 8.16, 32, .
..., the number of N-channel MOSFETs arranged in series in the vertical direction within the cell is 2'' (n≧2
) is efficient. In order to configure the ROM matrix with a small occupied area, it is desirable that n is large, but on the other hand, a configuration with a large n, that is, an N-channel MOSFE
In a configuration with a larger number of T, O3F between N channels
Since the isolation region between the ETs increases, the occupied area increases when a logic gate circuit or a static RAM is realized using such a cell with a large n. Therefore, normally a value of 2 to 3 is appropriate for n, but
In particular, when a gate array including a large number of ROMs is targeted, it is better to use a larger n value. Figure 3 is Figure 1(b)
2x4 gate array cells are arranged in an array, and 8
This is a circuit diagram configuring a ROM matrix 50 of bit x 8 words, where 100 is a cell and two P-channel MOS
It includes an FET and eight N-channel MOSFETs, and the address decoder 51, selector, and sense amplifier 52 are constructed using the same cell base pattern as 100 (FIG. 1(a)). 107 is a digit line, ROM
N-channel MOSFET in cell 100 according to the code
It is connected to the drain of the program wiring 110. 108 is a word line, which is an N-channel MO in the cell 100.
Connected to the gate of SFET.

By using the cell of the embodiment shown in FIG. 1(a), it is possible to realize a ROM cell for 8 bits, whereas the conventional cell shown in FIG. However, even the cell shown in Figure 6 consumes 81% of the area, which is equivalent to 4 bits (50%).
Therefore, the present invention has the effect of reducing the area occupied by the ROM in the gate array.

FIGS. 4(a) and 4(b) show an embodiment in which the present invention is applied to a gate isolation type gate array cell.

Gate isolation technology refers to adjacent MOSFE
Electrical isolation between Ts is achieved by fixing the potential of the gate electrode provided between them to the non-conducting side.
1892, pages 307 to 310. Since the electrical isolation region can be freely set in the metal wiring process, there is an advantage that it is possible to obtain a functional cell suitable for the circuit configuration and with less wasted area. FIG. 4(a) shows a gate-isolated basic cell 300 to which the present invention is applied, where n=2 as in FIG. 1(a), and one P-channel MOSFET and four It consists of N-channel MOSFETs of the same size. 301 is an N-type well;
302 is a P type diffusion layer, 303 is an N type diffusion layer, and 304 is a polysilicon film. FIG. 4(b) is a diagram when a ROM cell for 2×4 bits is constructed using four basic cells 300 of FIG. 4(a), and corresponds to FIG. 1(b). It is. In FIG. 4(b), 301 to 310 are 101 to 11 in FIG. 1(b), which is the first embodiment.
The part corresponding to 0 is shown. In FIG. 4(b), N-channel MO9FETs are arranged in four columns in the vertical direction.
Each of the N-channel MOSFETs belonging to the left and right columns of the columns is connected to a ground line 307a made of a first layer metal film through a contact 306, so that the polysilicon JI[304 forming the gate electrode is connected to the ground line 307a made of the first layer metal film. ,M
It is used as an electrical isolation element rather than an OSFET. On the other hand, a total of eight N channels M in the two rows in the center
In the OSFET, a polysilicon film 304 serving as a gate electrode is connected to a contact hole 3 between the polysilicon film and the first layer metal film.
06, a second metal film running in the vertical direction via the first metal film 307 and a through hole 309 between the first metal film and the second metal film
It is connected to a word line 308 made of a layered metal film, and a source electrode made of an N-type diffusion layer 303 is connected to a ground line 307a of the first layer metal film through a contact hole 305 between the diffusion layer and the first layer metal film. , the drain electrode is connected to a first layer which runs in the lateral direction by a program wiring 310 made of a first layer metal film, via a program terminal 307b made of a first layer metal film provided on the train diffusion layer according to the ROM code.
The connection to the digit line 307c made of a layered metal film is the same as in FIG. 1(b) in the first embodiment.

In this embodiment as well, the effect of reducing the area occupied by the ROM by applying the present invention is basically the same as in the first embodiment, without sacrificing the advantages of the gate isolation technology. That is clear.

〔Effect of the invention〕

As explained above, the present invention provides 2" (n≧2) for one P-channel MO8FET in a gate array cell.
N-channel MO with the same channel length and same channel width
Place SFET and use N-channel MOSFET to
By configuring the OM cell, it is possible to freely mount a high-density ROM in the gate array by simply changing the metal wiring pattern without sacrificing the advantages of the gate array. The present invention can be applied to both the conventional LOGO 8 isolation type and gate isolation type gate array cells, and is particularly applicable to a spread type gate array in which a plurality of gate array cells are arranged in an array vertically and horizontally. This is highly effective in increasing density by reducing the area occupied by the ROM in the array.

[Brief explanation of drawings]

FIG. 1<a) is a layout diagram showing a LOCO3 isolation type gate array cell of the present invention, and FIG.
Figure 1 (c) is a layout diagram including wiring when an 8-bit ROM cell is constructed using the one in (a), and a two-man NAND is constructed using the same one in Figure 1 (a). Layout diagram including wiring for the case, Figure 2 is similar to Figure 1 (a)
Figure 3 is a circuit diagram showing the structure of an 8-bit x 8-word ROM matrix; FIG. 4(a) is a second embodiment of the present invention, and FIG. 4(b) is a layout diagram showing the configuration when the present invention is applied to a gate isolation type gate array cell. A layout diagram including wiring when an 8-bit ROM is configured using a), Figure 5 is a layout diagram of a conventional gate array cell, and Figure 6 is a conventional static RAM realized in a small area. FIG. 3 is a layout diagram showing a gate array cell devised to enable the following. 100.200,300,400a,400b...Cell, 101,201,301,401-N type well, 1
02,201,301,402-P type diffusion layer, 103,
203, 303, 403/N type diffusion layer, 104, 204
, 304, 404... polysilicon film, 105, 30
5... Contact hole between the diffusion layer and the first layer metal film,
106, 306... Contact hole between polysilicon film and first layer metal film, 107... First layer metal film, 30
7a...Grounding wire, 307b-7o gram terminal, 30
7c, 107... Digit line, 108... Word line, 109° 309... Through hole between first layer metal film and second layer metal film, 110.310... Program wiring, door address decoder 2...Selector sense amplifier, 0...ROM matrix.

Claims (1)

[Claims] 1. One P-channel MOSFET and 2^n (n≧2)
N channels M with the same channel length and the same channel width
1. A gate array cell comprising at least one structural unit formed by arranging OSFETs in a row in the vertical direction. 2. 1 P-channel MOSFET and 2^n (n≧2)
N channels M with the same channel length and the same channel width
A first-layer metal film is formed in the horizontal direction on a bedded gate array base in which a plurality of gate array cells including at least one constituent unit formed by arranging OSFETs in a row in the vertical direction are arranged in an array in the vertical and horizontal directions. A word line made of a second layer metal film is arranged in the vertical direction of the digit line, and a program made of a first layer metal film is provided through a contact hole on the drain diffusion layer of the N-channel MOSFET in the gate array cell. 1. A ROM matrix for a spread-type gate array, characterized in that a ROM code is written depending on the presence or absence of a connection between a terminal and the digit line.