JPH03216996A - Image display device - Google Patents

Image display device

Info

Publication number
JPH03216996A
JPH03216996A JP2009924A JP992490A JPH03216996A JP H03216996 A JPH03216996 A JP H03216996A JP 2009924 A JP2009924 A JP 2009924A JP 992490 A JP992490 A JP 992490A JP H03216996 A JPH03216996 A JP H03216996A
Authority
JP
Japan
Prior art keywords
image display
display device
picture element
scanning circuit
horizontal scanning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009924A
Other languages
Japanese (ja)
Inventor
Shinichiro Hayashi
慎一郎 林
Atsuya Yamamoto
敦也 山本
Koji Senda
耕司 千田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2009924A priority Critical patent/JPH03216996A/en
Publication of JPH03216996A publication Critical patent/JPH03216996A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Abstract

PURPOSE:To dispence with conventional scanning ICs added later, to save a part mounting process resulting in decrease in a manufacturing cost and miniaturization of an image display device on the whole by manufacturing picture elements and scanning circuits on the same substrate. CONSTITUTION:On a translucent substrate 10, a picture element part 29 of thin film EL elements, and a vertical scanning circuit 30 and horizontal scanning circuit 31 which drive the picture element parts 29 are formed in a monolithic state. As the vertical and horizontal scanning circuits 30, 31 for driving the parts 29 are mounted on the same translucent substrate 10 with the picture element parts 29, a miniaturized image display device can be realized comparing with the conventional case where scanning ICs have to be added afterwards. The vertical and horizontal scanning circuits 30, 31 both can be produced at the same time as the picture element parts 29 eliminating the conventional mounting process.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は薄INIEL素子を用いた画像表示装置に関す
るものである. 従来の技術 近年、薄膜EL素子を用いた画像表示装1は軽量、薄型
、低消費電力などの特徴を有するフラットパネルディス
プレイとして、C R T ( CathodeRay
 Tube)では対応できない分野、たとえば、可搬型
計lllI機器の画像表示装置に用いられるなど、非常
に注目を集めている. 従来から用いられている薄IIEL素子を用いた画像表
示装置の画素部の基本的な構造を第4図に示す.これは
、ガラス基板41上の一方表面に、順次、直流スパッタ
装置を用いて製作したインジウム・スズ混晶酸化物(以
下、ITOと記す》による透明電極42と、高周波スバ
ッタ装置を用いて製作したSi02による第1誘電体層
43と、電子線蒸着法を用いて製作したZnSiMnに
よる発光層44と、高周波スバッタ装置と用いて製作し
たAQ2 03による第2誘電体層45と、蒸着装置を
用いて製作したAρによる背面電極46とがそれぞれ形
成されている構造である.このとき、透明電極42と背
面電極46とは互いに交差するようにストライプ状にフ
ォトリソグラフィーを用いて形成されている. 以上の薄膜EL素子を用いた画素部47には第5図に示
すように垂直走査用IC48と水平走査用IC49とが
外付けにより実装され、画像表示装置が製造される。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image display device using a thin INIEL element. BACKGROUND TECHNOLOGY In recent years, an image display device 1 using a thin film EL element has been developed as a flat panel display having characteristics such as light weight, thinness, and low power consumption.
It is attracting a lot of attention because it can be used in fields that cannot be covered by tubes, for example, as image display devices for portable meters. Figure 4 shows the basic structure of the pixel section of an image display device using conventionally used thin IIEL elements. This is made by sequentially forming a transparent electrode 42 made of indium tin mixed crystal oxide (hereinafter referred to as ITO) on one surface of a glass substrate 41 using a DC sputtering device, and a transparent electrode 42 made using a high frequency sputtering device. A first dielectric layer 43 made of Si02, a light emitting layer 44 made of ZnSiMn manufactured using an electron beam evaporation method, a second dielectric layer 45 made of AQ203 manufactured using a high frequency sputtering device, and a second dielectric layer 45 made of AQ203 manufactured using an evaporation device. The transparent electrode 42 and the back electrode 46 are each formed using the manufactured Aρ. At this time, the transparent electrode 42 and the back electrode 46 are formed in a stripe shape using photolithography so as to intersect with each other. As shown in FIG. 5, a vertical scanning IC 48 and a horizontal scanning IC 49 are externally mounted on a pixel section 47 using a thin film EL element, thereby manufacturing an image display device.

発明が解決しようとする課肋 しかしながら、上記従来構成では、垂直走査用IC48
および水平走査用IC49がガラス基板41外に外付け
で実装しているために、画素部47に比べて画像表示装
1が大きくなり、また、製造コストも高くなるという欠
点を有していた. 本発明は上記問題を解決するもので、小型でかつ、製造
コストが低減された薄膜EL素子を用いた画像表示装置
を提供することを目的とするものである. 課題を解決するための手段 上記問題を解決するために本発明は、薄膜EL素子を用
いた画像表示装置において、同一の透光性基板上にモノ
リシックに薄JflEL素予による画素部と、前記画素
部の駆動用の垂直走査回路および水平走査回路とを形成
したものである.作用 上記構成によれば、駆動用の両走査回路が同一基板上に
製造されるため、走査回路が基板外に外付けされている
ものに比べて画像表示装置全体の面積を小さくできる.
また、実装工程が省略できるので製造コストも低くでき
る. 実施例 本発明の一実施例について、図面を用いて説明する. 第1図は本発明の一実施例の画像表示装置の回路構成図
を示す平面図、第2図は第1図の画素部の要部拡大平面
図、第3図は第2図のE−F断面図である. まず、画素部29の構成およびその製造方法について説
明する.第3図に示すように、透光性を有する石英基板
などからなる透明基板10上に減圧CVD (Chel
Iical Vapor Deposition;以下
、CVDと記す。》法により厚さ0.2μm程度のポリ
シリコン層14を形成する.そして、フォトレジストを
マスクとして、プラズマエッチングによりトランジスタ
領域を形成した後、チャネル領域を形成するために、熱
酸化により厚さ0.1μm程度の酸化シリコン(Si0
2)層11を形成する.この上に、減圧CVD法により
厚さ0.3μm程度のポリシリコン層12を形成し、フ
ォトレジストをマスクとして、プラズマエッチングによ
りポリシリコン層12をバターニングすることにより、
ゲート電極と第2図に示すゲート信号練13とを形成す
る.この後、7才トレジストをマスクとして、ウェット
エッチングによりチャネル領域上に酸化シリコン層11
をバターニングし、ゲート酸化膜とする.次に、フォト
レジストをマスクとして、トランジスタ領域上に、P+
またはAs+をイオン注入し、ポリシリコン層14中に
n+領域であるソース領域14aとドレイン領域14b
とを形成することにより薄膜トランジスタを形成する.
そして、透明基板10上に、常圧CVD法により厚さ1
μm程度のs i o2層16を形成し、フォトレジス
トをマスクとして、反応性イオンエッチングにより、ソ
ースコンタクト用窓とトレインコンタクト用窓とを有す
る眉間絶縁展を形成する. さらに、透明基板10上に直流バイアススパッタ法によ
り厚さ1μm程度のAρ−SL合金膜を形成し、フォト
レジストをマクスとしたウエットエッチングにより、ソ
ース電極17とドレイン電極18とを形成すると同時に
、ソース信号線19と第1図に示すボンディングバヅド
20とを形成する.ここで、石英基板10上に、プラズ
マCVD法により厚さ0.3μm程度の窒化シリコン層
を形成し、フォトレジストをマスクとして、反応性イオ
ンエッチングにより、画素電極用窓とトレインコンタク
ト用窓とを有する第二の眉間絶縁J]ll21を形成す
る.そして、画素電極23として、たとえば、ITOな
どの酸化膜を用いるために、酸化展の作製時にドレイン
t[i18のAρ一St合金が酸化されないように、た
とえば、Crt!IやNi膜などの酸化されにくい金属
を、高周波マグネトロンスパッタ法により厚さ0.2μ
m程度トレイン電極18を覆うように形成した後、フォ
トレジストをマスクとして、ウエットエッチングにより
、コンタクト1122を形成する. その後、直流マグネトロンスバッタ法により厚さ0.1
μm程度のITO膜を形成した後、フォトレジストをマ
スクとしてウエットエッチングにより、画素電極23を
形成する.そして、この後、EL工程により、第1図に
示す画素部29をおおうように、順次S102による第
1誘電体層24、ZnSiMnによる発光層25、A1
203による第2誘電体層26、AρS1による背面電
極27を形成する. 最後にプラズマCVD装置により、窒化シリコンによる
保護膜28を防湿目的のために形成し、第1図に示すよ
うに、画素部29を形成する.また上述の薄膜トランジ
スタを形成するのに用いたC M O S ( Com
plementary Metal OxideSen
iconductor)プロセスにより、垂直走査回路
30と水平走査回路31とを透明基板10上に形成し、
これにより薄膜EL素子を用いたモノリシックの画像表
示装!を製遣する. なお、画素部29の薄膜トランジスタの耐圧を考慮して
、発光層25は低しきい電圧、たとえば、30■程度で
発光するものが望ましい.本実施例のように、発光層2
5にZnSIMnなどのZnS,CaSあるいはSrS
などを土成物とする無機系の薄膜EL素子を用いる場合
には、MBE(Morecular beam epi
taxy )装置やMOVPE(Metal orga
nic vapor phase epitaxy)装
置によるものが使用できる. 上記構成により、駆動用の垂直および水平走査回路30
. 31が画素部29と同一の透明基板10上に製造さ
れるので、従来のように外付けの走査用ICを用いる場
合に比べて、小型化された画像表示装置を実現でき、か
つ、両水平走査回路30. 31を画素部29と同時に
製造できて、従来行っていた実装工程が省略できる. なお、この実施例では画素部29の薄膜トランジスタと
して、P+やAs+をイオン注入したn型トランジスタ
を用いたが、B+をイオン注入したP型トランジスタで
もよい.すなわち、画素部29や垂直走査回路30や水
平走査回路31や薄膜トランジスタの構造は上記実施例
に限定されるものではない.tた、この実施例ではEL
工程において、二層の誘電体層を用いているが、一層だ
けでもよいし、発光層としてアルミノキノリン《8一h
yclroxy quinoline Alriinu
l)などの有機系の薄IglEL素子を用いてもよい。
Problems to be Solved by the Invention However, in the above conventional configuration, the vertical scanning IC 48
Also, since the horizontal scanning IC 49 is externally mounted outside the glass substrate 41, the image display device 1 becomes larger than the pixel section 47, and the manufacturing cost also increases. The present invention solves the above-mentioned problems, and aims to provide an image display device using a thin film EL element, which is small in size and has a reduced manufacturing cost. Means for Solving the Problems In order to solve the above problems, the present invention provides an image display device using a thin film EL element, in which a pixel portion formed by a monolithic thin JflEL element and the pixel are monolithically formed on the same light-transmitting substrate. This device includes a vertical scanning circuit and a horizontal scanning circuit for driving the parts. Effects According to the above configuration, since both scanning circuits for driving are manufactured on the same substrate, the area of the entire image display device can be made smaller compared to a case where the scanning circuit is externally attached to the outside of the substrate.
Additionally, since the mounting process can be omitted, manufacturing costs can be reduced. Embodiment An embodiment of the present invention will be explained with reference to the drawings. FIG. 1 is a plan view showing a circuit configuration diagram of an image display device according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of a main part of the pixel section in FIG. 1, and FIG. This is a cross-sectional view of F. First, the configuration of the pixel section 29 and its manufacturing method will be explained. As shown in FIG. 3, low pressure CVD (Chel
Iical Vapor Deposition; hereinafter referred to as CVD. >>A polysilicon layer 14 with a thickness of about 0.2 μm is formed by the method. Then, using a photoresist as a mask, a transistor region is formed by plasma etching, and then thermal oxidation is performed to form a silicon oxide (Si0
2) Form layer 11. On top of this, a polysilicon layer 12 with a thickness of about 0.3 μm is formed by low-pressure CVD, and the polysilicon layer 12 is patterned by plasma etching using a photoresist as a mask.
A gate electrode and a gate signal layer 13 shown in FIG. 2 are formed. After this, using the 7-year-old resist as a mask, wet etching is performed to form a silicon oxide layer 11 on the channel region.
is buttered to form a gate oxide film. Next, using the photoresist as a mask, a P+
Alternatively, As+ ions are implanted into the polysilicon layer 14 to form a source region 14a and a drain region 14b, which are n+ regions.
A thin film transistor is formed by forming .
Then, on the transparent substrate 10, a thickness of 1
An SIO2 layer 16 of approximately μm thickness is formed, and a glabellar insulating layer having a source contact window and a train contact window is formed by reactive ion etching using a photoresist as a mask. Further, an Aρ-SL alloy film with a thickness of about 1 μm is formed on the transparent substrate 10 by DC bias sputtering, and a source electrode 17 and a drain electrode 18 are formed by wet etching using a photoresist as a mask. A signal line 19 and a bonding pad 20 shown in FIG. 1 are formed. Here, a silicon nitride layer with a thickness of about 0.3 μm is formed on the quartz substrate 10 by plasma CVD, and a pixel electrode window and a train contact window are formed by reactive ion etching using a photoresist as a mask. A second glabellar insulation J]ll21 is formed. Since an oxide film such as ITO is used as the pixel electrode 23, for example, Crt! is used to prevent the Aρ-St alloy of the drain t[i18 from being oxidized during the fabrication of the oxide film. Metals that are difficult to oxidize, such as I and Ni films, are sputtered to a thickness of 0.2 μm using high-frequency magnetron sputtering.
After forming the contact 1122 so as to cover the train electrode 18 by about m, a contact 1122 is formed by wet etching using a photoresist as a mask. After that, a thickness of 0.1 was obtained using the DC magnetron scattering method.
After forming an ITO film with a thickness of approximately μm, a pixel electrode 23 is formed by wet etching using a photoresist as a mask. Thereafter, in an EL process, the first dielectric layer 24 in S102, the light emitting layer 25 in ZnSiMn, and the A1
A second dielectric layer 26 made of A.203 and a back electrode 27 made of A.rho.S1 are formed. Finally, a protective film 28 made of silicon nitride is formed for moisture-proofing purposes using a plasma CVD apparatus, and a pixel portion 29 is formed as shown in FIG. In addition, CMOS (Com
plementary Metal OxideSen
A vertical scanning circuit 30 and a horizontal scanning circuit 31 are formed on a transparent substrate 10 by a process (conductor),
This creates a monolithic image display device using thin-film EL elements! Manufacture and dispatch. Note that in consideration of the withstand voltage of the thin film transistor of the pixel portion 29, it is desirable that the light emitting layer 25 emit light at a low threshold voltage, for example, about 30 cm. As in this embodiment, the light emitting layer 2
5. ZnS such as ZnSIMn, CaS or SrS
When using an inorganic thin-film EL element using materials such as MBE (Molecular beam epi
taxi) equipment and MOVPE (Metal
(nic vapor phase epitaxy) equipment can be used. With the above configuration, the driving vertical and horizontal scanning circuit 30
.. 31 is manufactured on the same transparent substrate 10 as the pixel section 29, it is possible to realize a smaller image display device compared to the conventional case where an external scanning IC is used. Scanning circuit 30. 31 can be manufactured at the same time as the pixel section 29, and the conventional mounting process can be omitted. In this embodiment, an n-type transistor into which P+ or As+ was ion-implanted was used as the thin film transistor of the pixel portion 29, but a P-type transistor into which B+ was ion-implanted may also be used. That is, the structures of the pixel section 29, the vertical scanning circuit 30, the horizontal scanning circuit 31, and the thin film transistors are not limited to the above embodiments. In this example, EL
In the process, two dielectric layers are used, but it is also possible to use only one layer, or aluminoquinoline《81h
yclroxy quinoline Alriinu
An organic thin IglEL element such as 1) may also be used.

すなわち、発光層のしきい電圧が30V程度であれば薄
膜EL素子の構造、材料に特別に限定されないことは言
うまでもない. 発明の効果 以上のように、本発明の画像表示装置によれば、画素部
と走査回路とを同一基板上に作製するように構成したた
め、従来のように外付け走査用ICを用いないで済むの
で、実装工程を省略できて製造コストを低減できるとと
もに、画素部に対する画像表示装1全体の大きさ.を小
型化することができる.
That is, as long as the threshold voltage of the light emitting layer is about 30V, it goes without saying that there are no particular limitations on the structure or material of the thin film EL element. Effects of the Invention As described above, according to the image display device of the present invention, since the pixel portion and the scanning circuit are fabricated on the same substrate, there is no need to use an external scanning IC as in the conventional case. Therefore, the mounting process can be omitted and manufacturing costs can be reduced, and the overall size of the image display device 1 relative to the pixel portion can be reduced. can be made smaller.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の画素表示装置の回路構成を
示す平面図、第2図は同画像表示装置の画素部の要部拡
大平面図、第3図は第2図のE−F断面図、第4図は従
来の画像表示装置の画素部の要部断面図、第5図は同従
来の画像表示装置の平面図である.
FIG. 1 is a plan view showing the circuit configuration of a pixel display device according to an embodiment of the present invention, FIG. 2 is an enlarged plan view of essential parts of a pixel section of the image display device, and FIG. 3 is an E--E in FIG. 4 is a cross-sectional view of a main part of a pixel portion of a conventional image display device, and FIG. 5 is a plan view of the conventional image display device.

Claims (1)

【特許請求の範囲】[Claims] 1. 透光性基板上にマトリクス状に配列された薄膜E
L素子と薄膜トランジスタにより形成された画素部と、
前記画素部の駆動用の垂直走査回路および水平走査回路
とを備えるとともに、前記垂直走査回路および前記水平
走査回路が前記透光性基板上に前記画素部の薄膜トラン
ジスタを形成する工程で形成されている画像表示装置。
1. Thin film E arranged in a matrix on a transparent substrate
a pixel portion formed by an L element and a thin film transistor;
A vertical scanning circuit and a horizontal scanning circuit are provided for driving the pixel section, and the vertical scanning circuit and the horizontal scanning circuit are formed in a step of forming a thin film transistor of the pixel section on the light-transmitting substrate. Image display device.
JP2009924A 1990-01-19 1990-01-19 Image display device Pending JPH03216996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009924A JPH03216996A (en) 1990-01-19 1990-01-19 Image display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009924A JPH03216996A (en) 1990-01-19 1990-01-19 Image display device

Publications (1)

Publication Number Publication Date
JPH03216996A true JPH03216996A (en) 1991-09-24

Family

ID=11733635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009924A Pending JPH03216996A (en) 1990-01-19 1990-01-19 Image display device

Country Status (1)

Country Link
JP (1) JPH03216996A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002094064A (en) * 2000-09-11 2002-03-29 Matsushita Electric Ind Co Ltd Thin-film transistor, method for manufacturing the same, liquid crystal display device and electroluminescence display device
US7476900B2 (en) 1995-03-24 2009-01-13 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, organic electroluminescence display device and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7476900B2 (en) 1995-03-24 2009-01-13 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor, organic electroluminescence display device and manufacturing method of the same
JP2002094064A (en) * 2000-09-11 2002-03-29 Matsushita Electric Ind Co Ltd Thin-film transistor, method for manufacturing the same, liquid crystal display device and electroluminescence display device

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