JPH03214661A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03214661A JPH03214661A JP1019290A JP1019290A JPH03214661A JP H03214661 A JPH03214661 A JP H03214661A JP 1019290 A JP1019290 A JP 1019290A JP 1019290 A JP1019290 A JP 1019290A JP H03214661 A JPH03214661 A JP H03214661A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon layer
- high resistance
- resistance region
- polysilicon
- ultra
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 63
- 229920005591 polysilicon Polymers 0.000 claims abstract description 63
- 239000000758 substrate Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 abstract description 57
- 238000000034 method Methods 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 7
- 239000001257 hydrogen Substances 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 7
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 abstract description 4
- 239000001301 oxygen Substances 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 230000009545 invasion Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 8
- 230000001681 protective effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- -1 hydrogen ions Chemical class 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に半導体基板上に超高
抵抗ポリシリコン層を得るための構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure for obtaining an ultra-high resistance polysilicon layer on a semiconductor substrate.
第２図は従来の方法により形成された高抵抗ポリシリコ
ン層の断面図である。図において、１はシリコン基板、
２はポリシリコンの低抵抗領域、３はポリシリコンの高
抵抗領域、６はポリシリコンの酸化膜、７はスムースコ
ート等の絶縁膜、８はアルミ配線、９は保護膜としての
プラズマ窒化膜である。FIG. 2 is a cross-sectional view of a high resistance polysilicon layer formed by a conventional method. In the figure, 1 is a silicon substrate,
2 is a low resistance region of polysilicon, 3 is a high resistance region of polysilicon, 6 is an oxide film of polysilicon, 7 is an insulating film such as a smooth coat, 8 is an aluminum wiring, and 9 is a plasma nitride film as a protective film. be.
以下、高抵抗ポリシリコン層の形成方法を説明する。ま
ず、厚膜酸化膜上に、ＣＶＤ法によりポリシリコン層２
を形成し、次に、前記ポリシリコン層２に前記ポリシリ
コン層が所定の高抵抗値となるように、イオン注入法に
よりポロン及びリンを注入して高抵抗領域３を形成する
。A method for forming a high resistance polysilicon layer will be described below. First, a polysilicon layer 2 is deposited on the thick oxide film using the CVD method.
Next, a high resistance region 3 is formed by implanting poron and phosphorus into the polysilicon layer 2 by ion implantation so that the polysilicon layer has a predetermined high resistance value.
その後、前記の低抵抗領域２及び高抵抗領域３を有する
ポリシリコン層を熱酸化法により熱酸化し、表面を酸化
膜６で覆う。さらに、ＣＶＤ法により基板全面に厚膜の
層間絶縁膜７を形成する。Thereafter, the polysilicon layer having the low resistance region 2 and high resistance region 3 is thermally oxidized by a thermal oxidation method, and the surface is covered with an oxide film 6. Furthermore, a thick interlayer insulating film 7 is formed over the entire surface of the substrate by CVD.
次にコンタクト孔１０を形成し、さらに、該コンタクト
孔を埋めるようにアルミ配線を形成する。Next, a contact hole 10 is formed, and further, an aluminum wiring is formed so as to fill the contact hole.
そして最後に基板表面全面に保護膜としてプラズマ窒化
膜を形成する。Finally, a plasma nitride film is formed as a protective film over the entire surface of the substrate.
しかしながら従来の半導体装置では、上述の方法により
形成された高抵抗ポリシリコン層３は、その後の酸化及
び熱処理により膜厚あるいは膜質が大きく変化し、特に
保護膜としてのプラズマ窒化膜９中に含まれる水素イオ
ンにより大きく高抵抗値が変動することがよく知られて
いる。この高抵抗値の変化によりこの高抵抗値を用いた
デバイスの特性が変化し、特性の制御において大きな問
題が生じている。また、デバイス特性の向上とともに、
高抵抗を超高抵抗へ、さらに高度な制御技術がますます
要求されてくるが、従来の構造ではその対応が困難であ
った。However, in conventional semiconductor devices, the high-resistance polysilicon layer 3 formed by the above-mentioned method changes greatly in film thickness or film quality due to subsequent oxidation and heat treatment. It is well known that the high resistance value fluctuates greatly due to hydrogen ions. Changes in this high resistance value change the characteristics of devices using this high resistance value, creating a major problem in controlling the characteristics. In addition, along with improvements in device characteristics,
More and more advanced control technology is required to turn high resistance into ultra-high resistance, but it has been difficult to meet these demands with conventional structures.
この発明は、これらの問題点を解消するためになされた
もので、高抵抗値の変動を防止でき、よりよい制御が可
能である半導体装置を得ることを目的とする。The present invention has been made to solve these problems, and aims to provide a semiconductor device that can prevent high resistance value fluctuations and that can be better controlled.
〔課題を解決するための手段〕
本発明に係る半導体装置は、基板上に形成した第１層目
のポリシリコン層上に眉間絶縁膜を形成し、さらにその
上に上記第１層目のポリシリコンを完全に覆うように第
２層目のポリシリコン層を配置したものである。[Means for Solving the Problems] A semiconductor device according to the present invention includes a glabella insulating film formed on a first polysilicon layer formed on a substrate, and further a glabella insulating film formed on the first polysilicon layer. A second polysilicon layer is placed so as to completely cover the silicon.
本発明においては、前述のように第２層目ポリシリコン
層を、第１層目ポリシリコンで形成される超高抵抗領域
を完全に覆うように設けるようにしたので、超高抵抗を
形成した後の工程において、例えば酸化，熱処理中にお
ける酸素あるいは水素の超高抵抗領域への侵入が防止さ
れ、超高抵抗値の変動を防止することが可能となる。In the present invention, as described above, the second polysilicon layer is provided to completely cover the ultra-high resistance region formed by the first polysilicon layer, thereby forming an ultra-high resistance region. In subsequent steps, for example, during oxidation and heat treatment, oxygen or hydrogen is prevented from entering the ultra-high resistance region, making it possible to prevent fluctuations in the ultra-high resistance value.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による半導体装置において、
超高抵抗を形成した場合の断面図を示している。図にお
いて、１はシリコン基板、２は基板１上に形成した第１
層目ポリシリコン層の低抵抗領域、３“は第１層目ポリ
シリコン層の超高抵抗領域、４は眉間絶縁膜、５は２層
目ポリシリコン、６はポリシリコンの酸化膜、７はスム
ースコート等の絶縁膜、８はアルミ配線、９は保護膜と
てしてのプラズマ窒化膜、１０はコンタクト孔である。FIG. 1 shows a semiconductor device according to an embodiment of the present invention.
A cross-sectional view of a case where an ultra-high resistance is formed is shown. In the figure, 1 is a silicon substrate, and 2 is a first silicon substrate formed on the substrate 1.
3" is a low resistance region of the first polysilicon layer, 4 is an insulating film between the eyebrows, 5 is a second polysilicon layer, 6 is a polysilicon oxide film, and 7 is a low resistance region of the first polysilicon layer. An insulating film such as a smooth coat, 8 an aluminum wiring, 9 a plasma nitride film as a protective film, and 10 a contact hole.
以下、本実施例を製造工程に従って説明する。This example will be described below according to the manufacturing process.
図に示すように第１層目のポリシリコン層にて超高抵抗
領域３“と低抵抗領域２を形成する。尚、本実施例では
、超高抵抗値を得る方法として、第１層目のポリシリコ
ン層の薄膜化により対応している。その他の方法として
は、高抵抗長，１１，あるいはポリシリコン層への不純
物注入量の変更等により対応が可能である。また、第１
層目ポリシリコン層の超高抵抗領域３゛と、低抵抗領域
２はイオン注入量の差により形成する方法が一般的であ
る。As shown in the figure, an ultra-high resistance region 3'' and a low-resistance region 2 are formed in the first polysilicon layer.In this example, as a method of obtaining an ultra-high resistance value, This can be addressed by making the polysilicon layer thinner. Other methods include increasing the resistance length, changing the amount of impurity implanted into the polysilicon layer, etc.
The ultra-high resistance region 3' and the low resistance region 2 of the second polysilicon layer are generally formed by using a difference in the amount of ion implantation.
このようにして形成した第１層目のポリシリコン層をＣ
ＶＤ法により形成した層間絶縁膜である酸化膜４により
覆う。さらにこの層間絶縁膜４を介して、第１層目ポリ
シリコン層にて形成した超高抵抗領域３“を完全に覆う
ように第２層目ボリシリコン層５を配置する。この第２
層目ポリシリコン層５の不純物濃度は比較的低濃度が望
ましい。The first polysilicon layer formed in this way is
It is covered with an oxide film 4 which is an interlayer insulating film formed by the VD method. Further, a second polysilicon layer 5 is disposed via this interlayer insulating film 4 so as to completely cover the ultra-high resistance region 3'' formed of the first polysilicon layer.
The impurity concentration of the second polysilicon layer 5 is preferably relatively low.
それは、ポリシリコンのダレインの成長をおさえること
が、水素イオンの第１層目ポリシリコンにて形成される
超高抵抗領域への侵入を防止する効果が大きいためであ
る。また、超高抵抗領域３″を完全に覆うように配置し
た第２層目ポリシリコン層５の電位はある一定の電位に
固定することが望ましい。もちろん、この超高抵抗領域
３゛を完全に覆・うように配置された第２層目ポリシリ
コン層５はデバイスとしての配線の一部であってもよい
。This is because suppressing the growth of dalein in polysilicon has a great effect in preventing hydrogen ions from entering the ultra-high resistance region formed by the first layer of polysilicon. Furthermore, it is desirable to fix the potential of the second polysilicon layer 5, which is placed so as to completely cover the ultra-high resistance region 3'', to a certain constant potential. The second polysilicon layer 5 placed over and over may be part of the wiring as a device.
その後、第２層目ポリシリコン層５を熱酸化法又はＣＶ
Ｄ法により形成された眉間酸化膜６．７で覆う。この熱
酸化及びＣＶＤ酸化膜９形成時の酸素の侵入及び熱処理
に対しても、第２層目ポリシリコン層５は、第１層目に
より形成した超高抵抗領域３′の防御膜としての役割り
を果たしておりその効果は大きい。これにより、超高抵
抗値の変動は防止される。Thereafter, the second polysilicon layer 5 is formed by thermal oxidation or CV
Cover with glabellar oxide film 6.7 formed by method D. The second polysilicon layer 5 also plays a role as a protective film for the ultra-high resistance region 3' formed by the first layer against oxygen intrusion and heat treatment during thermal oxidation and CVD oxide film 9 formation. The effect is significant. This prevents fluctuations in the extremely high resistance value.
その後、第１層目ポリシリコン層の低抵抗領域２へのコ
ンタクト孔１０を形成し、さらにアルミ層により配線８
を形成する。Thereafter, a contact hole 10 to the low resistance region 2 of the first polysilicon layer is formed, and a wiring 8 is formed using an aluminum layer.
form.
その後、デバイスの保護膜として、基板全面にプラズマ
窒化膜９を形成する。その後、一般的には前記プラズマ
窒化膜９を形成してからは、形成時のダメージの低下及
びストレスの低下を目的として、低温（３５０〜４００
℃程度）の熱処理を行うことが多い。そしてこの熱処理
により、プラズマ窒化膜９中の水素イオンがもっとも大
きく超高抵抗値を変動させることが往々にしてあるが、
本実施例ではこの水素イオンに対しても、第２層目のポ
リシリコン層５により、その下層の超高抵抗領域である
第１層ポリシリコン層３“へ水素イオンが侵入するのを
防止でき、超高抵抗値の変動を防止できる。Thereafter, a plasma nitride film 9 is formed over the entire surface of the substrate as a protective film for the device. After that, generally after forming the plasma nitride film 9, the plasma nitride film 9 is heated at a low temperature (350-400°C) for the purpose of reducing damage and stress during formation.
Heat treatment is often performed at a temperature of around 30°F. Due to this heat treatment, hydrogen ions in the plasma nitride film 9 often cause the ultra-high resistance value to fluctuate the most.
In this embodiment, the second polysilicon layer 5 can prevent hydrogen ions from penetrating into the first polysilicon layer 3'', which is an ultra-high resistance region underneath. , it is possible to prevent fluctuations in ultra-high resistance values.
なお、本実施例においては、超高抵抗を第１層目ポリシ
リコン３１にて、その防御膜を第２層目のポリシリコン
５にて形成しているが、超高抵抗を第２層目のポリシリ
コンにて、その防御膜を第３層目のポリシリコンにて形
成してもよく、この場合においても上記実施例と同様の
効果を奏する。In this embodiment, the ultra-high resistance is formed by the first layer of polysilicon 31, and the protective film thereof is formed by the second layer of polysilicon 5, but the ultra-high resistance is formed by the second layer of polysilicon 5. The protective film may be formed of a third layer of polysilicon, and in this case, the same effects as in the above embodiment can be obtained.
以上のように本発明によれば、第１層目ポリシリコン層
により形成された超高抵抗領域上に、層間絶緑膜を介し
て第１層目のポリシリコン層を完全に覆うように第２層
目ポリシリコン層を設けるようにしたので、超高抵抗形
成以降の工程、例えば酸化，熱処理工程における酸素あ
るいは水素の超高抵抗層への侵入を防止でき、超高抵抗
値の変動を防止でき、超高抵抗値を精度よく制御できる
効果がある。As described above, according to the present invention, a layer is formed on the ultra-high resistance region formed by the first polysilicon layer so as to completely cover the first polysilicon layer through the interlayer insulation film. By providing a second polysilicon layer, it is possible to prevent oxygen or hydrogen from entering the ultra-high resistance layer during the steps after ultra-high resistance formation, such as oxidation and heat treatment, thereby preventing fluctuations in the ultra-high resistance value. This has the effect of accurately controlling ultra-high resistance values.
第１図はこの発明の一実施例による半導体装置の超高抵
抗部の断面図、第２図は従来方法による半導体装置の高
抵抗部の断面図である。
１・・・Ｓｉ基板、２・・・低抵抗領域、３・・・高抵
抗領域、３′・・・超高抵抗領域、４・・・第１層目ポ
リシリコン層一第２層目ポリシリコン層間の眉間絶縁膜
、５・・・第２層目ポリシリコン層、６・・・ポリシリ
コンの酸化膜、７・・・スムースコート等の絶縁膜、８
・・・アルミ配線、９・・・プラズマ窒化膜、１０はコ
ンタクト孔。
なお図中同一符号は同一又は相当部分を示す。FIG. 1 is a sectional view of an ultra-high resistance portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view of a high resistance portion of a semiconductor device according to a conventional method. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...Low resistance region, 3...High resistance region, 3'...Ultra high resistance region, 4...First layer polysilicon layer - second layer polysilicon layer Insulating film between the eyebrows between silicon layers, 5... Second polysilicon layer, 6... Polysilicon oxide film, 7... Insulating film such as smooth coat, 8
. . . aluminum wiring, 9 . . . plasma nitride film, 10 contact hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
半導体装置において、 前記基板上に形成された第１層目のポリシリコン層と、 該第１層目のポリシリコン層上に形成された絶縁膜と、 該絶縁膜上に前記第１層目のポリシリコン層形成領域を
覆うように形成した第２層目のポリシリコン層とを備え
たことを特徴とする半導体装置。(1) In a semiconductor device having a high-resistance polysilicon layer on a semiconductor substrate, a first layer of polysilicon layer formed on the substrate, and a layer of polysilicon layer formed on the first layer of polysilicon layer. A semiconductor device comprising: an insulating film; and a second polysilicon layer formed on the insulating film so as to cover a region where the first polysilicon layer is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019290A JPH03214661A (en) | 1990-01-18 | 1990-01-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019290A JPH03214661A (en) | 1990-01-18 | 1990-01-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03214661A true JPH03214661A (en) | 1991-09-19 |
Family
ID=11743426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1019290A Pending JPH03214661A (en) | 1990-01-18 | 1990-01-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03214661A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112410A (en) * | 1992-08-12 | 1994-04-22 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| KR100258493B1 (en) * | 1995-10-25 | 2000-06-15 | 가네꼬 히사시 | Semiconductor device having pesistor element and method of fabricating same |
-
1990
- 1990-01-18 JP JP1019290A patent/JPH03214661A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06112410A (en) * | 1992-08-12 | 1994-04-22 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| US5956592A (en) * | 1992-08-12 | 1999-09-21 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
| KR100258493B1 (en) * | 1995-10-25 | 2000-06-15 | 가네꼬 히사시 | Semiconductor device having pesistor element and method of fabricating same |
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