JPH03214246A - Replacing address generating circuit for cache device - Google Patents

Abstract

PURPOSE:To omit the cycle needed for access to an address having a mishit by generating an address so as to execute the replacement of the address having a mishit at the end of a replacement cycle. CONSTITUTION:When a signal, the inverse of RBCY 35 is set at a low level, a signal, the inverse of LOAD 32 is active. Then the values of addresses A2 and A3 are loaded as the initial values and the replacement is started at the value increased once. Then four replacement cycles are carried out with the outputs DA2(51) and DA3(52) set at 1 and 1, 0 and 0, 1 and 0 respectively. The values of both outputs are coincident with the values of addresses A2 and A3 in the four replacement cycles. Therefore a signal, the inverse of READY 36 is set at a low level in the 4-th replacement cycle. Thus a CPU 100 is ordered to read the data on an address where the CPU 100 has a mishit concurrently with the end of the 4-th replacement. Then the CPU 100 can start the next bus cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a replacement address generation circuit in a cache device.

[Conventional technology]

First, the cache device will be explained. A cache device is placed between a central processing unit (CPU) and a large-capacity main storage device, and is equipped with a controller and a high-speed cache device that manages the contents of the main memory so that it has copies of areas that are expected to be used frequently. consists of memory.

FIG. 8 shows an example of a system configuration using this cache device. The cache device 130 in this figure has a bus width of 3
It is assumed that 2 bits corresponds to 4 replacement cycles. The replacement address generation circuit 160 is included in the cache memory controller 140, and the cache device 130 consists of the cache memory controller 140 and the cache memory 150.
100 drives (outputs information to the bus)
address bus 102 of A4 or larger size
and information on the command bus 104, and the CPU 100
It is determined whether the data at the address to be accessed is stored in the cache memory 150 during read access.

When there is data in the cache memory 150, the information on the command bus A1B2 (main memory controller command bus) driven by the cache memory controller 140 causes the main memory controller 110 to prevent the main memory unit 120 from driving the data bus 101. READY36 is controlled to read data from the cache memory 150 at high speed based on the information on the command bus B133 (command bus for cache memory).
The bus cycle of the CPU 100 is ended by activating the .

When there is no data in the cache memory 150, a miss occurs and the cache device 130 tries to start a data replacement cycle.
The upper signal R1 (π 77 (main memory controller 1
When the main memory controller 120 outputs RACK 78 (response signal to RREQ 78 indicating that it is OK to start replacement) to command bus A 132 and command bus B 133, a replacement cycle is started. Output information for. Then, the cache data is stored from the main memory unit 120.
After data is transferred to the memory 150 for the number of replacement cycles and after fS, the data at the address that the CPU 100 attempts to access is read from the cache memory 150, READY36 is returned to the CPU 100, and the read cycle ends. The above CPU 100 performs memory read/
FIG. 9 shows an operation flowchart of the conventional cache device during a cycle.

Next, the conventional replace address generation circuit 160 of the cache unit 30 will be explained in detail. Here, an example will be explained in which the bus width is 32 bits and the number of bus cycles in the regrace cycle is four.

FIG. 10 is a circuit diagram of an example of a conventional replace address generation circuit, and FIG. 11 is a timing diagram showing the operation of the replace address generation circuit 160 of FIG. 10. Here, A2. of the address bus output from the CPU. A timing chart for replacement when a mishit occurs when the value of A3 is 0 or 1 is shown. This replacement address generation circuit 160 is a counter 10. Buffer A20° control circuit 30. It consists of a buffer B40.

σπ34 output from the control circuit 30 (“
The outputs IY1 (21) and IY2 (22) of the buffer A20 are controlled during cycles other than the replace cycle by a signal that controls the buffer B40 (low during the replace cycle and high at other times). Buffer B40 becomes active state in a high impedance inactive state (electrically isolated state), and address A
The values of 2 and A3 become the values of output DA2 (51: A2 to main memory and cache memory) and DA3 (52: A3' to main memory and cache memory), but buffer A20 is not activated during the replacement cycle. By setting the outputs 2Y1 (40) and 2Y2 (41) of the buffer B40 to a high impedance state, the QAII (QA ratio output of 10) and QB12 (QB output of 10) output from the counter 10 are The value is DA2 (51)
and the value of DA3 (52).

Next, the operation when a mishit occurs will be explained with reference to FIG.

First, an overview of the operation from when a cache miss occurs until replacement is performed will be explained.

When CPU ], 00 starts a bus cycle, B
CY72 (a signal that goes low while the CPU is in a bus cycle) goes low, and in the case of a cache range access, 63°73 (a signal that goes low while a cache range is being accessed) goes low, and the cache device When becomes low, it is determined that it is a cache access,
The R/W 74 (a signal that distinguishes between a read cycle (high) and a write cycle (low)) determines whether it is a read access or a write access. When this R/W 74 is high and addresses A2 to A31 (71: address output by the CPU) result in a miss, the cache device 130 starts a replacement cycle.

First, the cache device 130 activates RREQ77 (replace request signal), and the main memory controller 1
It waits for RACK78 (response signal to the RREQ signal), which is the response signal from 10, to go low. RACK
When 78 goes low, the cache device 130 outputs RBCY.
79 (a signal that goes low during a replace cycle) goes low to start a replace cycle. That is, when a miss occurs and replacement is ready, the cache device 130 sets RBCY79 to low, and this low starts the operation of the replace address generation circuit 160.

First, the control circuit 30 switches 0E34 from high to low, and the values of QAll and QB12 output from the counter 10 become the values of DA2 (51) and DA3 (52), and the control circuit 30 switches 0E34 from high to low. The counter 10 initializes the value of the counter 10 by setting the signal (signal for initializing the counter value) low.
The count is incremented in synchronization with the rising edge of the clock signal (clock input to the clock) switching from low to high. That is, if the values of DA2<51) and DA3 (52) are 0.0.0,
Four replacement cycles are performed with the values 1.1,1. The write strobe to the cache memory in the replace cycle is performed by σW76 (write strobe signal to the cache memory), and the data is written to the cache memory at the rising edge of CW76. By setting σ lower 34 high after the replacement cycle ends, DA2(
51) and DA3 (52) to the address values (A2 (1) and A3 (2)) where the CPU 100 caused a mishit.
value), CR75 (read strobe signal for cache memory) is set low to execute a cycle (hereinafter referred to as a cache reread cycle) in which the CPU 100 reads data at the address where the mishit occurred from the cache memory 150. , READY36
(READY signal to the CPU) is activated to terminate the cycle of the CPU 100 in which the mishit occurred.

[Problem to be solved by the invention]

As mentioned above, the conventional replace address generation circuit 16
0 means that the CPU 100 generates the address where the miss occurred after replacing the address in the block to be replaced, either in ascending order from the lowest address or in descending order from the highest address, regardless of the address that caused the miss. Then, a cycle (cache reread cycle) is required in which the CPU 100 accesses the data at the address where the miss occurred. After the replacement cycle after this miss, the cache
Since a re-read cycle is required, there is a problem that the CPU is kept waiting for a longer period of time when a mis-hit occurs, and the performance of the entire device is degraded.

An object of the present invention is to generate a replacement address so as to execute the replacement of a mishit address at the end of a replacement cycle, and to generate a replacement address when replacing Rf&.
To provide a replacement address generation circuit that eliminates the cache reread cycle after the completion of a replay race by causing the PU to also read the data at the address that caused the mishit and terminating the bus cycle that caused the mishit. be.

[Means to solve the problem]

The refinement of the present invention is to replace a cache device that replaces data between the main storage device and the cache device that occurs when a mishit occurs when the data at the address that the central processing unit attempts to access is not registered in the cache device. - The present invention is characterized in that the address generation circuit is provided with an address generation circuit that generates a replace address so as to replace the data of the address at the time of the miss at the end of the replace cycle.

In the present invention, the address generation circuit includes a control circuit that outputs a load signal and a switching signal for starting replacement in response to a replacement cycle signal from a cache device, and a control circuit that outputs a switching signal and a load signal for starting replacement in response to a replacement cycle signal from a cache device, and
It may include a counter that loads the address signal from U and starts counting from this point, and a buffer circuit that switches the output from this counter and the address signal by the switching signal and outputs it to the cache memory, The address signal to the counter may be an address obtained by increasing or decreasing the address signal from the CPU using a logical operation circuit.

〔Example〕

Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit block diagram of a replace address generating circuit according to an embodiment of the present invention, and the system configuration is that the replace generating circuit 160 in FIG. 8 is changed to a replace generating circuit 161. FIG. 2 shows the replacement address generation circuit of FIG. 1 with address A2. The value of A3 is 0.
FIG. 1 is a timing chart during a replacement cycle in the case of No. 1; Here, it is assumed that the cache device 130 has a bus width of 32 bits and the number of bus cycles in the replacement cycle is four. In this case, the operations other than the replacement cycle are the same as the conventional example shown in Figure 10, but the difference in operation when a mispit occurs is that the RBCY35 When it comes to low
Conventionally, the replacement cycle was started after initializing the counter value of the counter 10, but in this embodiment, the LOA
D32 (LOAD signal output to counter 10) becomes active and address A2. Counter 10 for the value of A3
Loaded as the initial value of DA2 (51
) and DA3 (52) values are 1.1.0. Four replacement cycles are performed with the value Oll, 0. At the fourth replacement, the values of DA2 (51) and DA3 (52) are changed to address A2. Since it matches the value of A3, in the conventional circuit, READY36, which was set to low during the cache re-read cycle, is set to low during the fourth replacement cycle in this embodiment, so that the fourth replacement is completed. At the same time, CPU100 also
reads the data of the address where the mishit occurred,
The CPU 100 bus cycle in which the mishit occurred is terminated, and cpuioo is enabled to start the next bus cycle immediately after the replacement cycle ends.

FIG. 4 is a circuit diagram of a replace address generation circuit 162 according to a second embodiment of the present invention. This embodiment is a circuit diagram when the bus width of the cache device 130 is 32 bits and the number of bus cycles in the replacement cycle is 8. Counter 10. The number of buffer 20.40 circuits is increasing.

The operation of this circuit is the same as in the first embodiment, and since the number of replacement cycles is 8, the address that the CPU 100 attempts to access during the 8th replacement cycle becomes the address that the CPU 100 attempts to access. READY36 goes low. Address A2 when a miss hit. A3. FIG. 5 shows the timing diagram of the replace cycle when the value of A4 (3: A4 of the address bus output by the CPU) is 0.1.1.

FIG. 6 is a circuit diagram of a replacement address generation circuit 163 according to a third embodiment of the present invention.
In order to bring the address from . ALLI60 from the information of A3 and the control signal 63 (CONTA) that controls whether the address is incremented or ticked.
is calculated. This ALU 6
The counter 10 loads the value of ACM (61, 62), which is the calculation result of 0, as the start value of the replace address. In this case, the cache device 130 has a bus width of 32
It is assumed that the number of bus cycles in the replace cycle is 4 in the bit.

FIG. 7 shows the replacement address generation circuit 163 of FIG. FIG. 4 is a timing chart during a replacement cycle when the value of A3 is 0.1. FIG. Since the ALU 60 increments the address by 1, the value that is incremented once after loading the counter value in the first embodiment becomes the counter value to be loaded in this embodiment, so the operation in this case is is the same as the operation of the first embodiment except for the operation of incrementing the counter value during the first replacement cycle.

As another example, 1. In the second embodiment, it is also possible to use the counter 10 as a down counter and start seven races using the value decremented once to sequentially down count the addresses. Further, in the third embodiment, the counter 1o is made a down counter, and the ALU 60
A similar effect can be obtained by generating an address that has been decremented from 1 to 1, and then starting the brenis with the value that has been decremented once, and counting down the addresses in order.

〔Effect of the invention〕

As explained above, the replace address generation circuit of the cache device of the present invention generates an address so that the replacement of a mishit address is executed at the first j[ of the replace cycle. A cycle in which the wait is released and the CPU can also read data, and the CPU accesses the address where the mishit occurred after the replacement cycle is completed (cache reread cycle)
This has the effect of eliminating the need for

[Brief explanation of drawings]

FIG. 1 is a block diagram of a replacement address generation circuit according to the first embodiment of the present invention, FIG. 2 is a timing chart at the time of replacing the one shown in FIG. 1, and FIG. 3 shows the operation of a cache device using this embodiment. FIG. 4 is a block diagram of a replacement address generation circuit according to a second embodiment of the present invention, FIG. 5 is a timing chart for replacing the one shown in FIG. 1, and FIG. 6 is a diagram of a third embodiment of the present invention. 7 is a timing chart for replacing the one shown in FIG. 6, and FIG. 8 shows an example of a system configuration using a general cache device. FIG. 10 is a block diagram of a conventional replacement address generation circuit, and FIG. 11 is a timing chart at the time of replacement of FIG. 10. 1 to 3...A2-A4 (address bus output by CPtJ), 4...Clock CLK input to the CPU and cache device, 10...Counter, 11 to 13.
・・QA~QC (output of counter 10), 20.40・
...Buffers A, B, 21-23.41-43-1.
Y 1~B (output of buffers 2o, 4o), 30...
・Control circuit, 31...ENB output to counter 1o
signal, 32... LOAD signal output to counter 1o, 33... cr output to counter 1o r=R(3
No. 34: σπ signal for controlling the five buffers A20 and B40, 35: RBCY signal from the cache device, 36: R E A for the CPU
D Y signal, 51-53...DA2-4 Address to main memory and cache memory, 60...ALU, 6
1.62...ACM2.3 (output signal from ALU60 to counter 10), 63...A[, control signal C0NTA for U3O, 71...A2 to A31 (CPU
), 72...BCY (signal that goes low during the CPU bus cycle), 73...C8 (
signal that goes low while accessing the cache range), 74
...R/W (signal indicating the type of CPU access (read/write)), 75...CR (read strobe signal for cache memory), 76...C
W (write strobe signal for cache memory)
, 77...RREQ (replace request signal to main storage device), 78...RACK (response signal to RREQ from main storage device to cache device), 79...
・DO~D31 (data on data bus), 100...
・CPU, 101...32-bit data bus, 102
...Address bus of A4 or larger, 103...A2A3
address bus, 104...command bus, 110...
...Main memory controller, 111... Main memory address bus, 112... Control bus C (control bus between main memory controller and main memory), 120... Main memory section, 13
o, Cache device, 131...DA2 DA3
address bar, 132... command bus A (command bus for main memory controller 1 to roller) 133... command bus B (command bus for cache memory), 14.
0...cache memory controller, 150...
. . . Cache memory, 160 to 163 . . . Replace address generation circuit.

Claims (1)

[Claims] 1. A cache device that replaces data between a main storage device and a cache device that occurs when a mishit occurs when data at an address that a central processing unit attempts to access is not registered in the cache device. Replacement of
A replace address generating circuit for a cuche device, characterized in that the address generating circuit is provided with an address generating circuit that generates a replace address so as to replace the data of the address at the time of the mishit at the end of a replace cycle. 2. The address generation circuit includes a control circuit that outputs a load signal and a switching signal for starting replacement in response to a replace cycle signal from the cache device, and a control circuit that loads the address signal from the CPU using the load signal from this control circuit. 2. A replacement address generation circuit for a cache device according to claim 1, comprising: a counter that starts counting from this point; and a buffer circuit that switches the output from the counter and the address signal using the switching signal and outputs the switched address signal to the cache memory. . 3. The replacement address generation circuit for a cache device according to claim 2, wherein the address signal to the counter uses an address obtained by increasing or decreasing the address signal from the CPU by a logic operation circuit.