JPH03201154A - Scsi host adaptor circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a SCSI host adapter circuit that performs DMA transfer between a host computer and a SCSI device, and is particularly suitable for use in a host computer that does not have a DMA restart function. The present invention relates to a SCSI host adapter circuit.

<Prior Art> FIG. 5 shows the configuration of a computer system having a 5C5I device. The host computer 1 includes a CPU 2,
A main memory 3 and a system bus 4 are included, and data is exchanged between the CPU 2 and the main memory 3 via the system bus 4 to execute predetermined processing. The host computer 1 also includes a system bus interface 5 and a channel bus 6, and is used to store and read data from and to a SCSI device 7 such as a magnetic tape or a magnetic disk. is connected to the SCSI bus 9, and this host adapter n8 is connected to the SCSI bus 9. For example, if the host computer
When reading data from the CSI device 7, use the SCS
DMA transfer is performed along the route I bus 9 -> host adapter circuit 8 -> system interface 5 -> system bus 4.

<Problems to be Solved by the Invention> However, when the host computer 1 does not have a DMA restart function, there is a problem that the throughput of the SCSI bus 9 decreases. In other words, while the SCSI bus 9 and the main memory 3 are performing DMA transfer, the SCSI device 7 is performing DMA transfer for track switching in a tape drive, etc.
Even if a request is made to temporarily suspend the transfer and release the SCSI bus 9, the host adapter circuit 8 rejects this request and disconnects from the SCSI bus 9 because the host computer 1 does not have a DMA restart function. had to be kept. Therefore, even though data transfer is not being performed, other devices cannot use the SCSI bus 9, resulting in a reduction in throughput and a problem in system performance.

Note that the DMA restart function is a function that allows DMA transfer to be temporarily interrupted and restarted, and is a function that allows the transfer start address to be reset at the time of restart.

<Object of the Invention> An object of the invention is to provide a 5cSI host adapter circuit that can receive a DMA interrupt request from a SCSI device and improve system performance.

Means for Solving the Problems> In order to solve the above problems, the present invention makes it possible to select a procedure using a data buffer or a procedure not using a data buffer as a DMA transfer between a channel bus and a SCSI bus. Then, DMA transfer between the channel bus and the data buffer and DMA transfer between the data buffer and the SCSI bus are performed successively, and after the data transfer in the data buffer is completed, when writing, issue an I/O request to the SCSI device, When reading data, the host computer issues a DMA request, the SCSI device interrupts the DMA, and when recombining, the DMA start address in the data buffer is shifted by the value specified by the SCSI device. be.

Effect> Even if the host computer does not have a DMA restart function, the SCSI bus can be released upon request from the SCSI device.

<Embodiment> FIG. 1 shows an embodiment of the SCSI host adapter circuit according to the present invention. In FIG. 1, /O is a data buffer composed of RAM; 1. One end of the second DMA bus 12 and one end of the third DMA bus 13 are set to Sa. 16 is a first bus selector to which the other end of the second DMA bus 12 and one end of the first DMA bus 11 are input, selects these, and outputs them to the fifth DMA bus 15.

17 is a channel bus control unit, which controls the fifth DMA bus 1;
5 is input. This channel bus control section 17 controls the channel bus 6. 18 is a second bus selector, to which the other ends of the third DMA bus 13 and the first DMA bus 11 are input, and selects these to select the fourth DMA bus 14.
1 and 19 output to the SCSI bus controller, and the fourth
DMA bus 14 is input. This SCSI bus control section 19 controls the SCSI bus 9. 20 is a CPU, which controls the entire system. 21 is a DMA I control unit, which controls the channel bus system v4 unit 17 and the data buffer/
D between O and data buffer lO and SCSI control unit 19
Controls MA transfer. From this DMA control unit 21, the first
Bus select signals 1 and 2 are output to the second bus selector 16.18. An address bus 22 connects the channel bus control section 17, DMA control section 21, data buffer/O, and SCSI bus control section 19. 23
is a data bus, and the channel bus control unit 17, DMA
The control section 21 and the SCSICS side control section 19 are connected. Furthermore, the control 0++ lines 1 to 3 are connected to the DMA control section 21 and the channel bus control section 17. Connects between the SCSI bus control unit 19 and data buffer/O. These control lines 1 to 3 are DM
It is used by the A control unit 21 as a handshake signal during DMA transfer.

Next, the operation of this embodiment will be explained based on FIGS. 2 and 3. In these figures, the portions surrounded by dotted lines are the features of the present invention. In FIG. 2, when there is a request from the host computer, a request reception process is performed, and when there is a reconnection, a request schedule is established and it is determined whether there is a request to be executed. When there is a request to be executed, it is determined whether the request is a request via the data buffer/O. It is a request via a buffer,
And if it is not a read request, DMA is sent to the host computer.
The channel bus 6 and data buffer/O
Activate the DMA between.

In other words, the second DMA is selected by the first bus selector 16.
Select a bus and perform DMA, when DMA is completed,
Or for a read request, select the SCSI device,
Performs command transmission processing and performs phase response processing until receiving a termination message.If there is no reconnection,
We will immediately move on to dealing with 7AIDS.

FIG. 4 is a flowchart showing the procedure of phase handling processing. This process has four phases: message out phase, message in phase, data phase, and status phase, and processes corresponding to each phase are performed.

In the message out phase, the message is transferred, and in the status phase, the status is received and the process ends.

In the message in phase, the process branches depending on the message after receiving the message. In the DMA pointer change message, the D in the data buffer T that performs DMA is
Shifts the MA start address by the specified value, which is
This is to perform DMA by shifting the address by the amount specified by the device when reconnected by the SCSI device. The shift value is notified by a message.

For a termination message, termination processing is performed, and for other messages, processing corresponding to that message is executed. In the data phase, depending on whether the request is via the data buffer/O and whether it is a read request, the following 4
It can be divided into two cases.

(1) If the request is via the data buffer/O and is a read request, activate DMA from the 5csr bus 9 to the data buffer/O. That is, the DM selects the third DMA bus with the second bus selector 18 and takes in the data on the SCSI bus 9 to the data buffer /O.
When A is finished, DMA is stopped and host computer 1
A DMA request is issued to DMA to start DMA between data buffer/O and channel bus 6, and when DMA is completed, DMA is
stop. Therefore, the first bus selector 16 selects the second DMA bus. In other words, the data on the SCSI bus is transferred to the data buffer/O by DMA and the SCSI
The I bus is released, and then DMA between the data buffer /O and the channel bus 6 is executed. Also, SCS
When the I-device stops DMA, it stops DMA.

(2) If the request is via the data buffer/O and is not a read request, the S from the data buffer/O
Executes DMA to the CSI bus 9. Therefore, the second DMA bus 12 is selected by the first bus selector 16. As explained in Fig. 2, the data to be written to the SCSI device has been transferred to the data buffer IO, so this data can be transferred to the SCSI bus 9. In this case as well, when the SCSI device stops DMA, , DMA
stop.

(3) In the case of a request that does not go through the data buffer/O, if it is a read request, DM to the host computer l.
A request is issued and DMA from the channel bus 6 to the SC3I bus 9 is executed. Also, if it is not a read request, S
Executes DMA from the CSI bus 9 to the channel bus 6. For these, first and second bus selectors 16.1
8 to select the first DMA bus. This operation is the same as the conventional example.

To summarize the above explanation, when DMA transfer via data buffer/O is specified, the second and third DMA buses are selected by the first and second bus selectors 16 and 18, and when it is not a read request, the second and third DMA buses are selected. is an I/O to a SCSI device
DM between channel bus and data buffer 1 before issuing a request
After executing A and once loading data into the data buffer/O, an I/O request is issued to the SCSI device to execute DMA between the data buffer/O and the SCSI device. Further, in the case of a read request, the data of the SCSI device is once taken into the data buffer /O, the device is disconnected, and then DMA is executed between the data buffer ylo and the channel bus. Further, when the SCSI device interrupts DMA, the DMA is stopped and the process is exited, and when the device reconnects with the device again, the DMA start address is shifted by the amount specified by the device and the DMA is activated. Data buffer/O
If DMA transfer via the first
, the first DMA by the second bus selector 16.18.
Select the bus and perform DMA transfer between the SCSI bus and the channel bus as usual.

<Effects of the Invention> As described above in detail based on the embodiments, the present invention allows DMA transfer via a data buffer and DMA transfer without via a data buffer.
MA transfer can be selected, the data to be transferred is once taken into the data buffer, and data transfer with the SCSI device is executed between the data buffer and the SCSI device. Therefore, even when reading data from a SCSI device that makes a DMA interrupt request, it is independent of the DMA with the host computer, so there is no need to reject the DMA interrupt request issued by this device. . Therefore, since the bus is no longer monopolized even when no data is being transferred, the throughput on the SCSI bus is improved.For example, in Figure 4, if there are tapes and disks as SCSI devices, , Conventionally, even if the tape requests DMA interruption at time T1 as shown in (A), the SC
Since the SI bus is not disconnected, the disk cannot be transferred as shown in (B), and disk access is completed at time T3. In contrast, according to the present invention, since the SCSI bus is immediately disconnected at T1 as shown in (C), the disk can immediately start data transfer as shown in (D). Therefore, the transfer can be completed at time T2.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the SCSI storage adapter circuit according to the present invention, FIGS. 2 and 3 are flowcharts for explaining its operation, and FIG. 4 is for explaining its effects. FIG. 5 is a configuration diagram of a conventional computer system. 6... Channel bus, 7... SCSI device, 9
...SCSI bus, /O...data buffer, 11
... first DMA bus, 12 ... second DMA bus, 13 ... third DMA bus, 14 ... fourth DM
A bus, 15...5th DMA bus, 16...1st DMA bus
bus selector, 17... channel bus control unit, 18
. . . second bus selector, 19 . . . SCSI bus control unit.

Claims (1)

[Scope of Claims] A data buffer; a first bus selector to which a DMA bus of the data buffer and a DMA bus not passing through the data buffer are input, and selects these buses and connects them to the channel bus; A DMA bus without a buffer and a DMA bus with a data buffer are input, and it has a second bus selector that selects these buses and connects them to the SCSI bus, and when DMA transfer via the data buffer is specified. , the DMA bus of the data buffer is selected by the first and second bus selectors to perform DMA transfer between the channel bus and the data buffer, and the DMA bus between the data buffer and the SCSI bus.
MA transfer is performed continuously, and after data transfer into the buffer is completed, an I/O request is issued to the SCSI device for writing, and a DMA start request is issued to the host computer for reading. This SCS is used when a device interrupts DMA and reassociates.
DMA in the data buffer by the value specified by the I-device
SC characterized by shifting the start address
SI host adapter circuit.