JPH03190422A - Input circuit - Google Patents

Abstract

PURPOSE:To attain the reception of a TTL signal and a low current consumption independently of the power voltage of this input circuit by inputting an input voltage to only one transistor(TR) and disposing a depression TR and a resistor in parallel at other TR. CONSTITUTION:TRs 3, 4 receiving a signal at its gate from an input terminal 1 are connected in cascade and the drain of the TR 3 is connected to a TR 6. Moreover, the depression TR 7 and the resistor 5 are connected in parallel with the TR 6 and a power voltage VDD is connected to the gate of the TR 7. The output of an inverter circuit 10 at the 1st stage is inputted to the gate of TRs 8, 9 of the inverter circuit 11 of a 2nd stage. The output terminal 2 of the inverter circuit 11 of the 2nd stage is connected to the gate of the TR 6 of the inverter circuit 10 of a 1st stage. Thus, a TTL(Transistor Transistor Logic) signal is received independently of the power voltage of the inverter circuits and the current consumption is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a monolithic IC input circuit, which serves as an interface for transmitting external control signals to internal circuits. be.

For example, CPU
When you want to control a certain kind of IC, such as NG Unit), it has the role of transmitting the control signal from the CPU to the certain kind of RC, and is often formed integrally with the certain kind of IC. It is something that will be done.

[Summary of the invention]

The present invention consists of a MOS transistor and a resistor, and the transmitting side (
For example, TTL (Transist
or Transistor Logic) level, that is, Low level can detect signals of 0.4 V or less, old gh level can detect signals of 2.4 V or more, and can do this with low current consumption.

[Conventional technology]

A circuit diagram of a conventional input circuit is shown in FIG. 2. When a TTL signal is input from input terminal 1, a complementary MO
The S invert circuit transmits the input signal to the next stage according to its inverted voltage level.

For example, if the inversion voltage of the invert circuit is designed to be around 1.5V, when 0.4V, which is the upper limit of the low level of the TTL signal, is input from the outside to input terminal 1, the output terminal 2 of the invert circuit will be , the power supply voltage of the invert circuit, VDD, that is, I (high level) is output. Conversely, when 2.4 V, which is the high level limit value of the TTL signal, is input to input terminal 1, the output of the invert circuit is , v5, which is the power supply voltage of the invert circuit, ie, Low level is output.

However, the circuit of FIG. 2 has the following drawbacks. When the power supply voltage of the invert circuit is higher than the TTL signal, consider, for example, the case where the power supply voltage of the invert circuit is about 15V and the TTL signal level is 5V at maximum.

When the input voltage exceeds the dark value voltage of the N-channel transistor of the invert circuit, both the P-channel and N-channel transistors are turned on, so 1ffi1!12i
t is V o o V s s I's'7 Ni'IQ
The current continues to flow until the input voltage rises below the threshold voltage of the P-channel transistor.

For example, if the threshold voltage of N-channel and P-channel transistors is 0.5V, the input voltage must be increased to 14.5V! The current flow will continue to be billions. That is, if a TTL signal of 5V is applied, a through current continues to flow, so a low current consumption cannot be used as an input circuit.

(Means for Solving Problem 18) The present invention aims to solve the problem L of the conventional technology, and is capable of receiving a TTL signal without depending on the power supply voltage of the invert circuit, and having low current consumption in the input circuit. We were able to realize this.

In terms of Jl, two sets of invert circuits having a CMOS configuration are connected in cascade, and the output of the invert circuit in the later stage is fed back to the gate of the transistor on one side of the invert circuit in the previous stage, and the depletion circuit is connected in parallel to the transistor on one side. A type transistor and a resistor are arranged, and two or more other transistors of the previous stage invert circuit are prepared,
It connects them in cascade.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a CMO3 type input circuit according to the present invention.

A signal is input from input terminal 1 to the gate of transistor 3.4. Transistors 3.4 are connected in cascade,
The drain of transistor 3 is connected to transistor 6. Further, a depletion type transistor 7 is connected in parallel with the transistor 6, and the gate of the transistor 7 is connected to the power supply voltage V. It is connected to the. The output of the first stage invert circuit 10 is sent to the second stage invert circuit 11.
The signal is input to the gate of transistor 8.9 constituting the circuit. The second stage invert circuit 11 has a simple CMOS configuration. The output terminal 2 of the second stage invert circuit 11 is connected to the gate of the transistor 6 in the first stage invert circuit 10.

Next, the circuit operation will be explained. Now, consider the case where input terminal 1 increases from zero voltage. At this time, transistor 3,
4 and 6 play the main role. There is no change in state until transistor 3.4 is turned on.

In this state, the output of the first stage invert circuit 10 is
The voltage at the connection point of transistors 3 and 4 is approximately ■ since the level is approximately V. As a result, a back gate effect acts on the transistor 3, and its dark value voltage increases. Therefore, even if a threshold voltage without the bank gate effect is applied to input terminal 1, transistor 3.4 will not turn on. Furthermore, since the gate voltage of transistor 6 is at the VSS level, transistor 6 will not turn on. Next, when the voltage at input terminal 1 is further increased, transistors 3 and 4 begin to turn on, and a through current begins to flow in the path of resistor 5 - transistor 6 - transistor 3 -> transistor 4. However, in the present invention, since the resistor 5 is inserted, the through current is considerably limited compared to that in FIG. When the voltage at the input terminal 1 is further increased and the output of the first-stage invert circuit 10 becomes Lo- level (■1.), the output terminal 2 of the second-stage invert circuit 11 becomes the old gh level (VDD ), which means that the signal at input terminal 1 is transmitted to output terminal 2. In this state, transistor 6 is turned off, and the through current path becomes resistor 5 - transistor 7 - transistor 3 - transistor 4. At this time, a back gate effect corresponding to the voltage drop due to the through current flowing through the resistor 5 acts on the transistor 7, so that the threshold voltage increases, and a self-suppressing effect that suppresses the through current acts on the transistor 7. As a result, the through current can be made sufficiently small.

Next, the operation in the reverse process of dropping the voltage at the input terminal 1 from that state will be explained. At this time, transistors 3, 4, and 7 play the main role.

Since the output of the first-stage invert circuit 10 is at Low level (Vss) as described above, the voltage at the connection point between transistors 3 and 4 is also at Low-level (■, s), and The bank gate effect does not work,
Therefore, the state of the output of the first stage invert circuit 10 will not change unless the input terminal 1 becomes lower than the dark value voltage of transistor 3゜4.If the voltage of input terminal 1 is further lowered, transistors 3 and 4 are turned off. Become. At this time, since the depletion transistor 7 is always ON, the output of the first stage invert circuit 10 changes to the old gh level (V, ). As a result, the second stage invert circuit 11 becomes Low.
The level is inverted to Vss, and the transistor 6 is turned on. This is the output terminal gh of the first stage invert circuit 10.
It has the effect of accelerating the

The above process is shown in Figure 3, where 4ia is the input voltage to the input l terminal, and the solid line is the second stage invert circuit
This is the output of As can be seen from Figure 3, when the input voltage rises from zero, it is inverted at voltage V, and when it falls, it is inverted at voltage v2, which is the hysteresis. Upper limit of level 0, 4
The constants of each transistor are designed so that V2 becomes 2.4 V, which is the lower limit of the TTL (7) old GH level.

〔Effect of the invention〕

As described above, according to the present invention, the input voltage is 0M0
Input only to one channel transistor of 8 circuits,
By arranging a depletion transistor and a resistor in parallel with the other channel transistor, the TT
Even if a t:rA lightning voltage higher than the L signal level is applied to the input circuit, the through current can be suppressed to a low level. Further, by inputting the output of the second-stage invert circuit to the other transistor of the first-stage invert circuit, it was possible to give the inverted voltage a hysteresis characteristic.

This has the effect of realizing an input circuit with low current consumption even if the power supply voltage of the input circuit and the input signal voltage are different.

Input circuit diagram FIG. 3 is an input/output characteristic diagram of the input circuit of the present invention.

3.4.6-9...MO'S transistor 5 ・ ・
・ ・ ・ ・ ・ ・ ・ more than Mr.

Claims (1)

[Claims] C consisting of an input terminal, an output terminal, and first and second conductivity types.
In a monolithic IC input circuit composed of MOS transistors, the input terminal is connected to all gates of a circuit in which a plurality of CMOS transistors are connected in cascade using MOS transistors of the first type, and MOS transistors of the second conductivity type are connected to each other. M, which has the same polarity as the second conductivity type MOS transistor and is a depletion type MOS transistor.
A first stage invert circuit configured by arranging OS transistors in parallel and inserting a resistor between the source side of the depletion type MOS transistor and the power supply, and inputting the output of the first stage invert circuit. a second stage invert circuit composed of CMOS transistors, and an output of the second stage invert circuit is input to the gate of a second conductivity type MOS transistor of the first stage invert circuit. Characteristic input circuit.