JPH03189767A - Design verifying device for logic circuit - Google Patents

Abstract

PURPOSE:To quickly confirm a desired time or a result of the nearest simulation thereto by displaying a result of simulation of the time concerned, when a specific time is designated, and displaying a result of the nearest time to its specific time, in the case there is no time concerned. CONSTITUTION:When a specific time of a result of simulation is designated by a retrieval object time designating means 8, a simulation result retrieving means 9 retrieves a result of the simulation concerned from a simulation result storage means 6 and displays it, and even if the one concerned does not exist, a result of simulation of the nearest time to the specific time is retrieved and displayed. In such a way, a desired time or a result of the nearest simulation thereto can be confirmed quickly.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a logic circuit design verification device that simulates a designed logic circuit and displays the resultant error value in an LSI logic circuit design verification system or the like. Regarding.

[Conventional technology]

Generally, the logic circuit design verification device as described above uses LS
The logic circuit designed by
By performing logical operations, the output signal that changes over time as the input signal changes is memorized as a simulation result, and the result can be displayed as a waveform or stored in a text file to display °0゛ and 1° ( or L° and °
This is a device that can display a list of logical value patterns of H'').

Then, the operator verifies whether the designed logic circuit is operating as desired based on the displayed simulation results, but the latter method of verifying the simulation results stored in a text file is difficult. (1) A method of expanding and displaying a text file with a text editor and verifying it using key operations.

(2) A method of displaying the contents of a text file using a type command (command for displaying the contents of a text file) and verifying it while stopping.

(3) How to print and verify a text file.

There are three ways.

In particular, method (1) examines how the output value of each signal line changes over time, but in doing so, there are cases where it is desired to display the output value of each signal line at a desired time. .

Conventionally, in such cases, a scroll function that moves the simulation results displayed on the screen one after another displays the results at the desired time, or a string function that searches for and displays the results corresponding to that time by specifying a time. to display the results at the desired time.

[Problem to be solved by the invention]

However, since the number of simulation results is usually large enough to span several thousand lines when displayed in a table, it is difficult to use the scroll function to move the results until the desired time appears. had the inconvenience that it took too long for the simulation results to be displayed on the screen.

Further, since the simulation results are stored every time the output value changes, the simulation results are not stored continuously every unit time from O in the text file.

Therefore, even if you searched for simulation results by specifying a time using the string function, if there was no data corresponding to that time, the results would not be displayed.

In that case, not only is the operation wasted, but the scrolling function must be used again, resulting in extra effort and effort.

The present invention has been made in view of the above points, and an object of the present invention is to quickly and reliably display simulation results for a desired time.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a simulation calculation means for simulating a designed logic circuit, a simulation result storage means for storing the results obtained by the means at each time the output value changes, and a display for displaying the simulation results. In the logic circuit design verification device, the logic circuit design verification device is equipped with a display device for searching the simulation result storage means for the simulation results corresponding to the specified specific time, and a time specifying means for specifying a specific time of the simulation result. a simulation result search means for reading a simulation result at a time closest to the particular time if there is no simulation result corresponding to the particular time; and a search result display means for displaying the retrieved simulation result on the display device. It has been established.

[For production]

In the logic circuit design verification device according to the present invention, when the time specifying means specifies a specific time for a simulation result, the simulation result search means searches and displays the corresponding simulation result from the simulation result storage means. Since the simulation results at the time closest to the specific time are searched and displayed even if there is no specific time, it is possible to quickly check the simulation results at the desired time or the simulation results closest to it.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 2 is a block diagram showing an example of the configuration of a logic circuit design verification apparatus according to the present invention. Storage device 2. Processing device 3. and a display device 4.

The keyboard 1 is an input device, and has character keys, number keys,
It is equipped with function instruction keys, etc., and provides instructions for executing a logic circuit simulation, and methods for displaying simulation results (methods of displaying simulation results as a list of logical values, a method of displaying them as waveforms, etc., which are the subject of this invention). ), input of time specification when displaying simulation results at a specific time in a list of logical values, and various other inputs. The storage device 2 is a hard disk device (HDD), etc. The circuit simulation results are stored for each time the signal name and output value change.

The processing device 3 is a microcomputer consisting of a CPU, ROM, RAM, etc., and controls the entire device, processes logical operations for simulating a logic circuit, and displays simulation results in various ways. The process of storing the simulation results in the storage device 2 in file format, the storage device! ! Processing to read simulation results stored in 2 into internal memory, processing to search for simulation results at a specific time, processing to search for simulation results at the closest time when there are no simulation results at a specific time, and processing to search for simulation results at the closest time. Performs display processing and other processing related to logic circuit simulation and display of simulation results.

The display device 4 is a display device such as a CRT or LCD, and displays simulation results, various work screens including a work surface for specifying a specific time, and other messages.

Next, the functions of the logic circuit design verification apparatus described above will be explained with reference to the functional block diagram of FIG.

First, when the simulation calculation means 5 of the processing device 3 simulates a logic circuit by logical operation,
Simulation result storage means 6 corresponding to storage device 2
stores the simulation results of the logic circuit in a file format, and the simulation result display means 7, which is the display device 4, displays the simulation results obtained by the simulation calculation means 5.

Next, when the file name of the simulation result stored in the simulation result storage means 6 and its specific time are entered using the search target time specifying means 8 of the keyboard 1, the simulation result retrieval means 9 of the processing device 3 searches. The simulation result of the file name inputted by the target time specifying means 8 is read from the simulation result storage means 6 and stored in the internal memory as a temporary file in three areas of signal name 9 hours and logical value, and the search target time is specified. The simulation results for the specific time inputted by the means 8 are retrieved from the temporary file and displayed on the search result display means 10 corresponding to the display bag W4.

Then, if there is no corresponding time in the search by the search target time specifying means 8, the simulation result of the closest time after the specific time is searched from the temporary file and displayed on the search result display means 10.

Next, the operating procedure and processing of simulation result verification by the logic circuit design verification apparatus of FIG. 2 will be explained with reference to the flowchart of FIG.

First, in step 1, when the user inputs and specifies the file name to be verified using the keyboard 1, the process proceeds to step 2, where the processing device 3 reads the simulation result of the specified file name from the storage device 2, and then proceeds to step 3. The signal name is 2 hours.

It is divided into three areas of logical values and expanded into the internal memory of the processing device 13 as a temporary file.

Next, after displaying the temporary file on the display device 4 in step 4, the process advances to step 5 and waits for input of an instruction for a function to display simulation results for a specific time.

In step 5, use keyboard 1 to input an instruction to display from the simulation results at a specific time, and in step 6
When a specific time is further designated and inputted, the process proceeds to step 7, where the processing device 3 searches for the designated time from the time area of the temporary file.

Then, in step 8, it is determined whether the corresponding time exists in the temporary file, and if so, the process proceeds to step 9 to display the simulation results for each time after the specified time, and returns to step 5.

If there is no corresponding time in step 8, proceed to step 10, search for the closest time after the input specific time,
In step 11, the simulation results for each time after the closest time are displayed, and the process returns to step 5.

If the instruction to display the simulation results at a specific time is not given in step 5, step 4 is performed in step 12. Step 9. The operator verifies the content of the simulation results displayed in step 11 from various angles using the cursor, and when all verifications are completed and the operator instructs the end of the work in step 13, the temporary file is closed and the simulation results are displayed. Finish the verification process.

Furthermore, if an instruction to continue the work is given in step 13, the process returns to step 5 and the verification is repeated.

Next, display of simulation results will be explained with reference to FIGS. 4 and 5.

FIG. 4 shows the screen 11 of the display device 4.
consists of a display area 11a that displays simulation result times and logical values, a command area 11b that has input areas for various commands including search commands, and designated times for search commands, and also has a help screen 11c.

FIG. 4 shows an example of the display state in step 4, in which the simulation results are displayed in the display area lla in order of the time at which the output value changed for each signal name.

Here, specify the search command 12 in the command area 11b, and input r to the specified time input a113 for a specific time, for example.
When 7000J is input, as a result of the search process described above, there is no data for that time r7000J, but if there is data for the closest time r7001J after that, then the time "7001J" is entered as shown in Figure 5. ” simulation results are displayed.

In this way, according to this embodiment, even if there is no corresponding input time, the simulation result of the closest time after that time is displayed, so that the operation of specifying a specific time is not wasted.

In addition, in the above example, if there is no simulation result corresponding to a specific time, the result at the closest time after that specific time is displayed, so the time required for searching can be minimized. , it is convenient to display the simulation results of the closest time before or after a specific time, since it is convenient to see the simulation results before and after the time specified in - degrees, and the simulation results of the closest time regardless of before or after the specific time are displayed. It would be even more convenient to display the results.

〔Effect of the invention〕

As explained above, the logic circuit design verification device according to the present invention displays the simulation results for the specified time when a specific time is specified, and if there is no corresponding time, the result for the time closest to the specified time is displayed. , so you can quickly check the simulation results at or closest to the desired time.

Therefore, the simulation results of the logic circuit can be verified efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the functional configuration of the embodiment shown in FIG. 2 of the present invention, FIG. 2 is a block diagram showing the configuration of a logic circuit design verification apparatus which is an embodiment of the present invention, and FIG. is a flowchart showing the operating procedure and processing of simulation result verification according to this embodiment, and FIGS. 4 and 5 are explanatory diagrams of display examples of simulation results on the display device. 1...Keyboard 2...Storage device 3...
Processing device 4...Display device 5...Simulation calculation means 6...Simulation result storage means 7...Simulation result display means 8...Search target time designation means 9...Simulation result search means 10. ...Search result display means 11...Screen 11a...Simulation result display area 11b...Command area

Claims (1)

[Scope of Claims] 1. Simulation calculation means for simulating the designed logic circuit, simulation result storage means for storing the results obtained by the means for each time the output value changes, and displaying the simulation results. A logic circuit design verification device comprising: a time specifying means for specifying a specific time of the simulation result; and a simulation result storage means for storing the simulation result corresponding to the specific time specified by the means. a simulation result search means for searching and reading out a simulation result corresponding to the specific time, and reading out a simulation result at a time closest to the specific time if there is no simulation result corresponding to the specific time; and displaying the simulation result searched by the means on the display device. 1. A logic circuit design verification device comprising: search result display means for displaying search results.