JPH03188520A - Dma data transfer control circuit for magnetic disk - Google Patents

Dma data transfer control circuit for magnetic disk

Info

Publication number
JPH03188520A
JPH03188520A JP1327169A JP32716989A JPH03188520A JP H03188520 A JPH03188520 A JP H03188520A JP 1327169 A JP1327169 A JP 1327169A JP 32716989 A JP32716989 A JP 32716989A JP H03188520 A JPH03188520 A JP H03188520A
Authority
JP
Japan
Prior art keywords
magnetic disk
data transfer
timer
dma data
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1327169A
Other languages
Japanese (ja)
Inventor
Hidekazu Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP1327169A priority Critical patent/JPH03188520A/en
Publication of JPH03188520A publication Critical patent/JPH03188520A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a stable counted value by delaying the start of DMA data transfer to a magnetic disk by a hard timer.
CONSTITUTION: When the transfer data volume is inputted to a DMA (direct memory access) controller 2 and a computing element 11, the value obtained by the computing element 11 is inputted to a timer 12 and the timer 12 is started. When a write command is set to a magnetic disk controller 5, DMA data transfer between a buffer 4 and the magnetic disk is tried but data transfer is not executed because a write enable signal from the magnetic disk controller 5 to the magnetic disk is masked by the timer 12. When the timer 12 expires, the write enable signal is made effective, and DMA data transfer between the buffer 4 and the magnetic disk is started to transfer data from the buffer 4 to the magnetic disk. Thus, the stable counted value is obtained.
COPYRIGHT: (C)1991,JPO&Japio
JP1327169A 1989-12-19 1989-12-19 Dma data transfer control circuit for magnetic disk Pending JPH03188520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1327169A JPH03188520A (en) 1989-12-19 1989-12-19 Dma data transfer control circuit for magnetic disk

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1327169A JPH03188520A (en) 1989-12-19 1989-12-19 Dma data transfer control circuit for magnetic disk

Publications (1)

Publication Number Publication Date
JPH03188520A true JPH03188520A (en) 1991-08-16

Family

ID=18196078

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1327169A Pending JPH03188520A (en) 1989-12-19 1989-12-19 Dma data transfer control circuit for magnetic disk

Country Status (1)

Country Link
JP (1) JPH03188520A (en)

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