JPH03186018A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To reduce the power consumption by controlling the circuit current of a comparison part between two of comparison parts which compare reference voltages corresponding to respective quantization levels with an input signal and are arranged in parallel by using the differential output between the two comparison parts. CONSTITUTION:Differential preamplifiers A1-A16 compare the reference voltages corresponding to the quantization levels generated by resistors R1-R6 and the analog signal from a terminal 22 and amplify their differences and control circuits D1-D16 are driven with their outputs. High-speed is required by a parallel type A/D converter, so its current is large, but the currents of ECL circuits of comparators C1-C16 are controlled to increase the constant current of parts where the reference voltages and analog input signal are nearly equal and decrease the current of parts where the difference are large. Consequently, the power consumption is reduced.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to an analog-to-digital converter (hereinafter referred to as an AD converter), and particularly a parallel type AD converter with low power consumption.
Regarding converters, conventional technology is shown in Fig. 3, which is a block diagram of a 4-bit parallel type AD converter with reduced power consumption, disclosed in Japanese Patent Publication No. 61-738.
L R1-R16 is a resistor that creates a reference voltage for comparison.
Even if six resistors with the same resistance value are connected in series, A1
-A16 is the front differential amplifier C1-C16 is the comparator D
i-Di6 includes pre-differential amplifiers A1 to A16 and comparator C1
-Control time 1 to control the current of C16! Ll
~L15 is the AND of the comparator output 23 is the hexadecimal 4
Encoder matrix input for converting into bits B1-B
4 is an output buffer - 1M5B-LSB is a 4-bit digital output terminal 21 is a reference voltage terminal, 22 is an analog signal input terminal, 24 is a clock signal input terminal, and 25 is a 180 degree phase shifter depending on the clock input signal. In the conventional parallel AD converter configured as described above (with a circuit that generates clocks of different φ and φ), each reference voltage corresponding to each quantization level generated by the resistors Rl-R16 and the terminal Analog signal from 22 (above) Even though the difference is always compared and amplified by the front differential amplifier Al-Al6, this output is used by the control circuits D1 to D.
Even if 16 is driven, the parallel AD converter requires high speed, so the power exchange is large.The current of the ECL circuit of comparators C1 to C16 is controlled to maintain a constant current of approximately equal parts of the reference voltage and analog input signal. In the comparison area where the reference voltage and analog input signal are almost equal, the analog input signal is near the reference voltage of this comparator. Therefore, it is necessary to improve the speed and accuracy of the comparator in this vicinity. Therefore, the ECL of this comparator is
On the other hand, in the comparator part where there is a large difference between the reference voltage and the analog input signal, the comparison speed is fast and the accuracy of the comparator is high. It is good that it is low (1, so it is rather EC
Sufficient response speed can be obtained even if the constant current of L is reduced, but on the other hand, the output of the pre-differential amplifier A1-A16 is input to the comparator Cl-C16.
If the input signal is slightly lower than the voltage at the contact point of resistors R14 and R15, the output of the comparator will be C.
Up to 14 can be “1” and C15 to C16 can be “0”.
Therefore, only the AND of the output of the comparator C14 and the inverted version of the output of C15 becomes I+1'', and the AND circuit L1
This output is converted into a 4-bit signal by the encoder matrix 23, and the output buffer outputs "1" from B2 to B4 at the timing of clock φ.
'', a binary signal of ``1110'' is output to the output terminal and held until the next timing. In the parallel AD converter of this type, the current of the ECL circuit is controlled L, and a large current flows only in one part, so power consumption can be significantly reduced. However, in the 4-bit AD converter described in Figure 3, the comparator However, with an AD converter of about 10 bits, there is no significant effect, and the problem that the invention aims to solve. The current of the pre-differential amplifier and the comparator connected to it tends to be slow based on the output of the dynamic amplifier. An object of the present invention is to provide a parallel-type AD converter, but it is also an object of the present invention to solve the above-mentioned problems. It has means for controlling a circuit current of a comparison section located between the two comparison sections using differential outputs of two comparison sections among a plurality of comparison sections arranged in parallel that compare a reference voltage and an input signal. The present invention is also applicable to an analog-to-digital converter characterized by the above-mentioned structure. If the polarities of the outputs are different, the differential input of the comparator placed between them is small, and by increasing the current source of this comparator, the speed can be increased.Embodiment FIG. 1 shows one embodiment of the present invention. 4-bit parallel type A in the example
This shows the constituent countries of the D converter. &R1 to R16 are resistors that create a reference voltage for comparison, and even though 16 resistors with the same resistance value are connected in series, Al-Al6 is a pre-differential amplifier.
Compare C1 to C16! , DI-016 is a control circuit that controls the current of the pre-differential amplifier and comparator! Ll-L1
5 is an AND circuit of the comparator output. 23 is an encoder matrix input that converts hexadecimal to 4 bits. B1 to B4 are output buffers. MSB-LSB are 4-bit digital output terminals. 21 is a reference voltage terminal. Reference numeral 22 denotes an analog signal input terminal, and the operation of the parallel AD converter of this embodiment configured as above will be explained below. Even though the difference between the reference voltage of the reference voltage and the analog signal 1 from the terminal 22 is constantly compared and amplified by the pre-differential amplifier Al-Al6, this output is used to control the circuits D1 to D16.
Even if the parallel AD converter is driven, high speed is required, so the current of the ECL circuit of the power exchange comparator CI-Cl6, which has a large current, is controlled to maintain a constant current of approximately equal parts of the reference voltage and analog human input signal. The power consumption is reduced by increasing the current and reducing the current in the portion where the difference is large. In the comparison part where the reference voltage and analog input signal are almost equal, the analog input signal is near the reference voltage of this comparator, so it is necessary to improve the speed and accuracy of the comparator in this vicinity.Therefore, the ECL of this comparator is On the other hand, in the comparator part where there is a large difference between the reference voltage and analog input signal, it is necessary to increase the constant current in the circuit and increase the response speed. The accuracy of the converter is also low (Xo) Therefore, even if the constant current of the ECL is reduced, a sufficient response speed can be obtained. A specific example of the control circuit will be shown.R,
-R,.4 is a resistor that creates a reference voltage for comparison, and five resistors having the same resistance value are connected in series. 51-60 are load resistances 41-5o are differential amplification transistors 4
AII=Aa-i is a pre-differential amplifier, for example A1
1 is a load resistance 51, 52 and a differential amplification transistor 41
．． It consists of 42 pieces. D n ”” D n + a
is the pre-differential amplifier A n −A n *4 and the comparator C
61 to 69 and 161 to +69 are transistors that control the currents of n to Cn+1, and transistors 61 to 69 determine the operating currents.The current control circuit includes, for example, P channel MOS transistors Dn and transistors 61 and 161. The reference voltage and input signal are configured as one unit, and the pre-differential amplifier circuit AII-A,
For example, when the reference voltage terminal 21 is set to a negative reference voltage and the differential amplification transistors 45 and 46 are balanced (the collector potential of the upper transistor 44 is high and the collector potential of the transistor 48 is low), The Vow of the P-channel MOS transistor 66 becomes negative, and the source and drain become conductive, increasing the base potential of the transistor 65 forming a constant current circuit and causing the currents of the differential amplification transistors 45 and 46 to flow.At the same time, the base potential of the transistor 165 increases. As described above, in a comparator where the reference voltage and the input signal are equal, the current in the constant current circuit is large, and in a comparator where the difference between the reference voltage and the input signal is large, the current in the comparison section Cn+* can also be increased. The current is low
Although this current control is always performed and depends on changes in the analog human power signal, in this embodiment it is possible to control the power signal using a differential output before and after a comparison section. Multiple comparators are combined into one to reduce power consumption due to current in the toll circuit.
The parallel type of the present invention may be controlled by multiple current control circuits (because the current does not need to be strictly suppressed, and it is sufficient that the current is greater than or equal to the current at which the circuit operates stably). According to the AD converter, a large current flows only in the comparator section where a reference voltage close to the human input signal is applied, so power consumption can be reduced with a simple method in a high-bit parallel AD converter. Therefore, the present invention is applicable to monolithic ICs where power consumption is a problem.
It is also a very effective method for

[Brief explanation of drawings]

FIG. 1 shows the configuration of a parallel AD converter according to an embodiment of the present invention. FIG. 2 shows the circuit configuration of the device of the same embodiment.
The figure is a configuration diagram of a conventional low power consumption parallel AD converter.

Claims (1)

[Claims] In analog-to-digital converters using parallel comparison method,
A circuit of a comparison section located between the two comparison sections using the differential outputs of two of the plurality of comparison sections arranged in parallel to compare the reference voltage corresponding to each quantization level and the input signal. An analog-to-digital converter, characterized in that it has means for controlling current.