JPH03184098A - Method and device for adaptive conversion encoding - Google Patents

Abstract

PURPOSE:To compress auxiliary information and to improve the encoding quality by varying block length by using the difference between blocks of the conversion coefficient obtained by converting an input signal linearly. CONSTITUTION:The best block length is selected by using the difference between blocks of the conversion coefficient obtained by linear conversion with the block length and the conversion coefficient corresponding to the best block length is quantized to transmit information. Namely, the conversion coefficient corresponding to the best block length and the auxiliary information are selected by selectors 28 and 29 and supplied to a quantizer 4, a bit distributing circuit 6, and a multiplexing circuit 15 respectively. The bit distributing circuit 6 performs bit distribution by using the conversion coefficient supplied from the selector 28 and the quantizer 4 uses the obtained bit distribution information to quantize the conversion coefficient supplied from the selector 28. The quantized conversion coefficient and bit distribution information are multiplexed by the multiplexing circuit 15 with the best block length and the dispersion value of the input signal and sent out to a transmission line 8. Consequently, the auxiliary information is compressed to improve the encoding quality.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to band compression technology for signals such as voice/music, and in particular to band compression technology that performs band compression after linearly converting an input signal obtained in the time domain to another domain. Regarding technology.

(Prior art) Bandwidth compression is the process of reducing the amount of information contained in signals such as voice/music in order to efficiently transmit the information contained in signals such as voice/music using lines with limited transmission capacity. Differential pulse code modulation [AD PCM] (digital
Coding on Waveforms, (Di
Digital Coding of Waveforms
), Prentice Hall Co.
See e-Ha 11), 1984, p. 308;
Below, “Reference IJ) and adaptive transform coding [ATC]
(IBEE TRANSACTIONS ON ANISP)
ON ASSP) Volume 27, No. 1, 1979, 89-95
See page; hereinafter referred to as "Reference 2") is known. The outline of ATC will be briefly explained below according to Document 2.

FIG. 4 is a block diagram showing an example of the configuration of the ATC. In an encoder comprising linear transformation, bit allocation, and quantization, an input signal is supplied to a linear transformation circuit 3 via an input terminal 1. In general, discrete values are supplied to the input terminal l, and a linear transformation circuit 3 performs N-point discrete linear transformation in units of input samples equal to a predetermined integer N. N is called the block length. As this N-point discrete linear transformation,
Walsh-Hadamard transform (WAT), discrete Fourier transform (DFT), discrete cosine transform (DCT), KL inverse transform (KLT), etc. are used. The total number N of transform coefficients output from the linear transform circuit 3 are each quantized by a quantizer 4 according to a bit allocation to be described later, and then supplied to a multiplexing circuit 5. The quantizer 4 includes a number of quantizers equal to the block length N, and each transform coefficient is quantized by a dedicated quantizer. The bit allocation circuit 6 calculates the quantization bit allocation corresponding to the amplitude of the transform coefficient and supplies it to the quantizer 4. The multiplexing circuit 5 multiplexes the quantized transform coefficients supplied from the quantizer 4 and the information used for bit allocation supplied from the bit distribution circuit 6, and sends the multiplexed information to the transmission line 8.

In the decoder, which consists of bit allocation, inverse quantization, and linear inverse transformation, the multiplexed signal from the transmission line 8 is separated by the separation circuit 9, and the signal from the quantizer 4 is sent to the inverse quantum vase lO, and the signal is sent to the bit allocation circuit. The signal from 6 is supplied to bit allocation circuit 11. The bit allocation circuit 11 determines the bit allocation for each transform coefficient in exactly the same manner as the bit allocation circuit 6 of the encoder.

The transform coefficients dequantized by the dequantizer XO according to the bit allocation determined by the bit allocation circuit 11 are converted again into a total number N of time domain signal samples by the linear inverse transform circuit 12, and are sent to the output terminal 14. Supplied.

There are several types of allocation methods in bit allocation circuits, but here we will use the method described in Document 2 as the fifth method.
This will be explained with reference to Figures (a) and (b).

This method minimizes the squared quantization error when dequantized in the decoder. In order to reduce the amount of auxiliary information regarding bit allocation, the transform coefficients are thinned out once, and then the interpolated values are Optimize the number of bits using The bit allocation circuitry shown in FIG. 4 is as shown in FIG.
). The conversion coefficients obtained by the linear conversion circuit 3 in FIG. 4 are supplied to the thinning circuit 42 via the input terminal 41 in FIG. 5(a). The thinning circuit 42 squares each of the N conversion coefficients, and thins out 17H using the average value of each integer value M (M is a divisor of N) as a representative value. The obtained sample value of L=N/H is sent to the quantizer 43
are respectively quantized by the output terminal 44 and the inverse quantizer 45.
supplied to The quantizer 43 and inverse quantizer 45 may be omitted in some cases. In the interpolation circuit 46, after taking the base-2 logarithm, M times linear interpolation is performed in the logarithm domain. Using the interpolated signal, the bit allocation in the quantizer 4 in FIG. 4 is determined by the bit number optimization circuit 4 according to the following formula.
It will be held at 7.

Here, R1 is the i-th conversion coefficient (i=1.2...
. . N), 100 is the average number of bits allocated per one conversion coefficient, and σ12 is the square value of the i-th conversion coefficient approximately restored by interpolation in the interpolation circuit 46. The result is transmitted to the output terminal 48 and fed to the quantizer 4. IEE Transactions on AnisSP (IEE Transactions on ANISP) has shown that the squared quantization error can be minimized by allocating bits using equation (1).
IEEE TRANSACTI○NS ON AS
SP) Vol. 25, No. 4, 1977, pages 299-309; (hereinafter referred to as "Reference 3"). The thinned signal obtained at the output terminal 44 is sent to the transmission line 8 as auxiliary information via the multiplexing circuit 5 shown in FIG. On the other hand, the bit allocation circuit 11 shown in FIG. 4 is configured as shown in FIG. 5(b). The signal from the separation circuit 9 of FIG. 4 is supplied to the interpolation circuit 46 via an input terminal 49. The bit allocation circuit 6 in the encoder includes a quantizer 43 and an inverse quantizer 45
, the bit allocation circuit 11 in the decoder also has a corresponding inverse quantizer 45. The interpolation circuit 46 and the bit number optimization circuit 47 perform the same interpolation and bit number optimization as the interpolation circuit 46 and the bit number optimization circuit 47 in the encoder described above.

Therefore, signals for completely equal bit allocation are obtained at the output terminal 48 in FIG. 5(a) and the output terminal 50 in FIG. 5(b), and corresponding signals are obtained on the encoder and decoder sides. quantization/inverse quantization is performed.

In the explanation so far, the signal supplied from the bit allocation circuit 6 to the multi-electrification circuit 5 as auxiliary information is the square value of the thinned-out conversion coefficient obtained at the output terminal 44 in FIG. 5(a). However, the purpose of transmitting this signal to the decoder is to share approximate values of transform coefficients used for bit allocation between the encoder and the decoder. As methods for transmitting auxiliary information for this purpose, methods using PARCOR coefficients, ADPCM, vector quantization, and the like are known in addition to the square value of thinned-out transform coefficients.

In the encoder, the input signal can also be normalized for the purpose of obtaining transform coefficients whose amplitude does not depend on the power of the input signal at the output of the linear transform circuit 3 of FIG. In this case, as shown in FIG. 6, the input signal is normalized through the normalization circuit 2 and then supplied to the linear conversion circuit 3. In the decoder, the output of the linear inverse transform circuit 12 is subjected to processing opposite to that of the normalization circuit 2 in the inverse normalization circuit 13, and then sent to the output terminal 1.
4. The reference value used for normalization is the multiplexing circuit 5
The signal is multiplexed with the signals from the quantizer 4 and the bit allocation circuit 6, and is transmitted to the decoder via the transmission path 8.

On the decoder side, the signal is separated from the signal supplied to the dequantizer 10 and bit allocation circuit 11 by the separation circuit 9, and then transmitted to the denormalization circuit 13. FIGS. 7(a) and 7(b) show the configurations of the normalization circuit 2 and the denormalization circuit 13, respectively.

The input terminal 61 in FIG. 7(a) has the input terminal l in FIG.
The input signal samples are provided by

After the input signal samples are temporarily stored in buffer 62,
The N samples are collectively scaled by a multiplier 63 and supplied to an output terminal 65. The output signal t from the output terminal 65 is supplied to the linear conversion circuit 3 shown in FIG.

The multiplier of the multiplier 63 is the reciprocal of the average value of the input sample power for one block. This value is the reciprocal of the variance for an input signal with an average of zero, and can be calculated from the variance value determined by the variance calculation circuit 64. The variance value determined by the variance calculation circuit 64 is used by the multiplier 63 to normalize the input sample, and at the same time is supplied to the multiplexing circuit 5 in FIG. 6 via the output terminal 66, and after multiplexing, It is conveyed to the decoder as auxiliary information. On the other hand, in the inverse normalization circuit shown in FIG. 7(b), the signal from the linear inverse transform circuit 12 shown in FIG. 6 is supplied to a multiplier 68 via an input terminal 67. The multiplier 68 denormalizes the output signal using the dispersion value obtained through the input terminal 69 and stores it in the buffer 70 . The dispersion value obtained at the input terminal 69 is transmitted to the multiplexing circuit 5 in FIG.
, transmission line 8 and separation circuit 9, and is transmitted from the encoder. Buffer 70 sequentially stores N decoded sample values.
The signal is transmitted to the output terminal 14 in FIG. 6 via the output terminal 71.

(Problem to be Solved by the Invention) The number of blocks N affects the resolution of calculations performed in the linear transformation circuit 3 and linear inverse transformation circuit 12 shown in FIGS. 4 and 6, and the larger N is, the higher the resolution is. Errors caused by encoding and decoding are reduced. Further, the auxiliary information regarding bit allocation is inversely proportional to the number of blocks included in a certain period of time, and the larger N is, the more the amount of auxiliary information is reduced. This means that more main information can be sent for a given transmission capacity, leading to improved encoding quality. On the other hand, for non-stationary signals, a large N does not necessarily give a small error. This is because although the same processing is performed on input samples within the same block, if the block is long, the characteristics of the non-stationary signal t may change within the same block.

Therefore, for signals with strong non-stationarity, it is better to perform encoding that follows changes in the properties of the input signal using a small block length N. In conventional ATC, block length N
Since the resolution was fixed, it was not possible to meet the conflicting demands of resolution and ability to follow changes in the properties of the input signal.

An object of the present invention is to provide an adaptive transform encoding method and apparatus that can improve encoding quality by compressing the amount of auxiliary information while satisfying the conflicting demands of resolution and tracking changes in the properties of input signals. There is a particular thing.

(Means for Solving the Problems) The present invention performs linear transformation using the specified block length when the block length is specified, and otherwise stores input signal samples in a buffer. , performs linear transformation with a plurality of block lengths, stores the obtained transform coefficients and auxiliary information independently, and at the same time calculates inter-block differences of transform coefficients corresponding to the plurality of block lengths, and calculates the plurality of block lengths. determining an optimal block length using the ratio of the inter-block differences corresponding to the lengths of two adjacent blocks when arranged in order of size and the inter-block differences; and determining the stored transformation corresponding to the optimal block length. Coefficients and auxiliary information are selected, the selected transform coefficients are quantized by bit allocation calculated using the transform coefficients, and the quantized output, bit allocation information, and the selected auxiliary information are It is characterized by transmission/storage with optimal block length.

The present invention also provides a buffer for accumulating input samples, a linear transformation circuit for performing linear transformation with a plurality of block lengths, a first storage device for storing obtained transformation coefficients, and a first storage device for storing obtained transformation coefficients. a second storage device for storing auxiliary information obtained by the conversion process; a difference detection circuit that receives the transformation coefficients corresponding to a plurality of block lengths and outputs an optimal block length using inter-block differences of the transformation coefficients; and the difference detection circuit. a first selector that receives an optimum block length supplied from the first storage device and a block length designation signal supplied from the outside and selects an output according to the block length designation signal; a second selector that selects a value corresponding to the output of the first selector; and a third selector that receives the output of the second storage device and selects the value that corresponds to the output of the first selector. , a bit allocation circuit that calculates bit allocation for the transform coefficients based on the output of the second selector, and quantizes the transform coefficients selected by the second selector according to the bit allocation obtained by the bit allocation circuit. comprising at least a quantizer, a multiplexing circuit that multiplexes and transmits/stores the output of the first selector, the output of the quantizer, the output of the bit allocation circuit, and the output of the third selector; The difference detection circuit includes a switch that switches input transform coefficients according to a plurality of block lengths, a plurality of storage devices connected to the plurality of output terminals of the switch, and one of the outputs of the plurality of storage devices. a subtracter for subtracting the output of the selector from the input conversion coefficient; a multiplier for squaring the output of the subtracter; an accumulator for accumulating the output of the multiplier; a third storage device that stores the output of the accumulator; a maximum value detection circuit that determines the maximum value from a plurality of outputs of the third storage device; and a fourth storage device that stores the output of the maximum value detection circuit. a divider for calculating the ratio of two data among the plurality of outputs of the fourth storage device; a fifth storage device that stores the output of the divider; and an output of the fifth storage device. an optimal block length selection circuit that determines an optimal block length using the third storage device; a sudden change detection circuit that receives a plurality of outputs from the third storage device and detects a significant change among the plurality of outputs; It is characterized by comprising a fifth selector that selects and outputs either the output of the optimum block length selection circuit or the output of the sudden change detection circuit according to the output of the detection circuit.

(Operation) There is a correlation between signal properties and the distribution of transform coefficient components, and signals with similar properties have similar transform coefficient component distributions. This is also true for transform coefficients in multiple blocks extracted from the same signal. Therefore, by monitoring the difference in transform coefficients between adjacent blocks and using a block length that reduces the difference, it is possible to satisfy the contradictory demands of resolution and tracking changes in the properties of the input signal.

The adaptive transform encoding method and apparatus of the present invention can adapt to changes in resolution and properties of input signals by making the block length N variable using inter-block differences in transform coefficients obtained by linearly transforming an input signal. It is possible to improve the encoding quality by compressing the amount of auxiliary information while satisfying the conflicting demands of tracking the auxiliary information.

(Example) Next, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, if a block length is specified, encoding is performed using the specified block length, otherwise, linear transformation is performed on the input signal, and the obtained transformation coefficients are used to perform encoding. The optimal block length is determined and encoding is performed using the optimal block length. For this purpose, storage device 25.2
6, selectors 27, 28, and 29, a difference detection circuit 36, and a block length designation signal input terminal 17.

When no input signal is supplied to the block length designation signal input terminal 17, the input signal supplied to the input terminal 1 is normalized by the variance value of the input signal in the normalization circuit 2 using one block length candidate N1. be done.

The normalized signal is subjected to N1-point discrete linear transformation in the linear transformation circuit 3, and then stored in the storage device 25 and simultaneously supplied to the difference detection circuit 36. Further, the variance value used for normalization is stored in the storage device 26. Next, normalization and linear transformation are performed on the samples equal to the second block length N2 in the same manner as in the case of N1, and the results are stored in the storage devices 25 and 26 and supplied to the difference detection circuit 36. . In the same manner as in the cases of N1 and N2 explained above, normalization and linear transformation using the input signal are performed for the cases of multiple block lengths N3, N4, ...N, and the corresponding transformation coefficients and variance values are are stored in the storage circuits 25 and 26, and the conversion coefficients are also supplied to the difference detection circuit 36. However, normally N, < N 2 < N 3 < N 4...
...Nn, and 2N, =N, (1≦i<n). Block length N1, N2, N3, N4,...N
When all the calculations of the transform coefficients for n are completed, the difference detection circuit 36 calculates the transform coefficient y for each block length candidate value N, (1≦i<n); (Nl) (j=1...N,
) and the value z; (J) one block before that, the sum δ(N1) of the squared differences between blocks of the transform coefficients is calculated. Optimal block length N using δ(N,)
m is selected and supplied to the selector 27. Selector 2
7 is also supplied with a block length selection signal. When the block length selection signal is supplied, the selector 27 selects the block length selection signal, and otherwise selects the optimal block length Nm supplied from the difference detection circuit 36, and outputs the selected signal.

The output signal of the selector 27 causes the selectors 28 and 29 to
, the transform coefficients and auxiliary information corresponding to the optimal block length Nm are selected, the transform coefficients are sent to the quantizer 4 and the bit allocation circuit 6, and the dispersion value of the input signal, which is the auxiliary information, and the optimal block length Nm are sent to the multiplexing circuit. 15, respectively. The optimal block length Nm is quantized and then sent to the multiplexing circuit 1.
5 may be transmitted. The bit allocation circuit 6 performs bit allocation using the transform coefficients supplied from the selector 28, and uses the obtained bit allocation information to allocate bits to the quantizer 4.
quantizes the transform coefficients supplied from the selector 28. The quantized transform coefficients and the bit allocation information are multiplexed with the optimum block length Nm and the dispersion value of the input signal in the multiplexing circuit 15, and sent to the transmission line 8.

When an input signal is supplied to the block length designation signal input terminal 17, the selector 27 selects the supplied block length N9 and sets it to the optimum block length Nm. Therefore, subsequent quantization is performed based on the supplied block length N9. Next, referring to FIG. 2, an actual procedure for selecting an optimum block length will be described, taking as an example a case where an optimum block length is determined from n types of block lengths. Here, to simplify the explanation, we will use n=3 as shown in Figure 2.
(Select the optimal block length from three different block lengths)
Assume that

Let time 1=0 be the time when the encoder starts operating. At time N1T (T is the sampling period), N1 input signal samples are accumulated in the buffer in the normalization circuit of FIG. This state is shown in (A) of FIG. 2(a). In the figure, the input signal sample indicated as N 1 (t), that is, the hatched portion indicated as I, is subjected to linear transformation with block length N1, and the transformation coefficients are stored in a storage device. At time N2T, samples equal to the second block length N2 (N1<N2) are accumulated in the buffer. This situation is shown in FIG. 2(a)-(B).

At this time, the input signal sample indicated as N (2) in the same figure, that is, the hatched part indicated as ■, is subjected to linear transformation with a block length of N.
Furthermore, for the input signal sample labeled N2(1), that is, the hatched portion labeled ■ and the hatched portion labeled ■, a block length N2 is added.
A linear transformation is performed according to the equation, and each transformation coefficient is stored in a storage device. At time (N1+N2)T, samples equal to N1+N2 are accumulated in the buffer. This state is shown in (C) of FIG. 2(a). At this time, the input signal sample indicated as N in the same figure (3), that is, the hatched part indicated as ■, is subjected to linear transformation with a block length of N, and the transformation coefficients are calculated. Furthermore, at time N3T, the third block length N 3 (N 1 < N 2 < N 3
) are accumulated. This situation is shown in Figure 2 (
Shown in (D) of a).

At this time, linear transformation with block length N1 is performed on the input signal sample indicated as N (4) in the same figure, that is, the hatched part indicated as ■.
In addition, the input signal samples indicated as N2(2), that is, the hatched portion indicated by ■ and the hatched portion indicated by ■, are subjected to linear transformation using the block length N2, and further Linear transformation with block length N3 is performed on the input signal samples indicated as N5(1), that is, the hatched portions indicated as ■, ■, ■, ■, and the respective transformation coefficients are stored in the storage device. Store. Hereinafter, N1(1) stored in the storage device,
Conversion coefficients corresponding to N1(2), Nt(3), N1(4), conversion coefficients corresponding to N2(1) and N2(2),
Using the transform coefficients corresponding to Determine Nm.

The above processing procedure is summarized in FIG. 2(b). N
Taking the case of 3=2 N 2=4 N t as an example, the maximum block length N3 can be expressed by four minimum block lengths N1: ■, ■, ■, ■. Linear transformation using block length N1 for the input data of the blocks of ■, ■, ■, ■ is performed in the blocks of ■, ■, ■, ■'', respectively. The linear transformation using length N2 is
This is done in blocks marked with and ■°. Furthermore, ■＋■
Block length N for input data of blocks of 10■+■
A linear transformation using 3 is performed in the block of I'. Therefore, in block I'', which has the largest amount of processing, ■
Linear transformation using block length N, for I+IV, linear transformation using block length N2 for I+n+II
[Linear transformation using block length N3 for +IV, and inter-block differences δ(N,), δ(N2) of transformation coefficients
, δ(N3) and use these to determine the optimal block length Nm. That is, it is assumed that the time required for all these processes is shorter than N and T.

As is clear from FIG. 2(b), the buffer in the normalization circuit 2 must have a capacity of at least N3T, and is reset every N3T. Transform coefficients corresponding to the selected optimal block length are taken out from the storage device in N3 samples at a time, quantized by the quantizer 4, and then sent to the transmission line 8 in FIG. Therefore, as shown in FIG. 2(C), the data sent to the transmission path 8 has consecutive blocks of the same length in units of N3. Hereinafter, this block length will be referred to as a unit block. Next, referring to FIG. 3, the difference detection circuit 36
The operation will be explained in detail.

FIG. 3 shows details of the difference detection circuit 36. A signal supplied from the linear conversion circuit 3 in FIG. 1 is supplied to the input terminal 301, and a signal from the output terminal 314 is transmitted to the selector 27. The conversion coefficients supplied to input terminal 301 are input to switch 302, selector 304, and subtracter 305. Each output terminal of the switch 302 has storage devices 3031, 3032, . . . , 303. is connected. Storage device 3031.303°,...
303n corresponds to block lengths Ni, N2, ..., Nn, and 3031 indicates the conversion coefficient zz of one block before.
(Nt - t) (J = ■...N,) is stored. The selector 304 selects these storage devices 303
□, 303°, ..., 303. One of the outputs is selected and transmitted to the subtracter 306. switch 302
and selector 304 are both controlled by the conversion coefficients supplied to input terminal 301. The output of the selector 304 is subtracted from the transform coefficient supplied to the input terminal 301 by a subtracter 305, and the result is supplied to a multiplier 306. That is, when a transform coefficient corresponding to a certain block length N1 is supplied to the input terminal 301, a transform coefficient corresponding to N; l block before is selected by the selector 304, and the transform coefficient corresponding to the block length N;
01 is subtracted from the transform coefficients of the current block by a subtractor 305. At the same time, the current transform coefficients are stored in the storage device 3031 connected by the switch 302. Multiplier 306 squares the inter-block difference of the transform coefficients supplied from subtracter 305 . The calculations so far are performed for each transform coefficient. The obtained inter-block difference square values are accumulated in an accumulator 307, and the sum of the inter-block difference square values of transform coefficients for all transform coefficients is determined.

Hereinafter, this will simply be referred to as an inter-block difference in transform coefficients. The inter-block difference of the transform coefficients output from the accumulator 307 is
It is calculated for each unit block and stored in the storage device 308.

Maximum value detection circuit 309 detects the maximum value of inter-block differences of transform coefficients corresponding to each block length candidate value for each unit block, and stores it in storage device 310. That is, for each unit block, the storage device 310 stores as many maximum inter-block differences of transform coefficients as there are block length candidate values.

The division circuit 316 uses these maximum values max (δ(Ni)) supplied from the storage device 310 to calculate adjacent maximum values max (δ(Ni):) and max (δ(N++)
t)) ratio δR(i)=maX(δ(NiJ)/ma
x(δ(Ni))--(3) is calculated for l≦i≦n-1 and stored in the storage device 315. max (・)
is the maximum value operator.

The optimal block length selection circuit 311 determines the optimal block length using these ratios δ3(i) supplied from the storage device 315, and transmits the determined optimal block length to the selector 313. The optimal block length selection circuit 311 searches for i giving m1n(:δR(i)) for 1≦i<n−1, and determines the optimal block length Nln by setting m=i.

min (·) is the minimum value operator.

Furthermore, in parallel, a sudden change detection circuit 312 detects a sudden change in the input signal characteristics using the difference between transform coefficient blocks, and unconditionally selects the minimum block length when a sudden change is detected. This is performed by the selector 313 selecting a signal supplied to the selector 313 from the sudden change detection circuit 312 and transmitting the selected signal to the output terminal 314. A sudden change in the input signal characteristics is detected by comparing the values of δ(N1) obtained from the storage device 308. The storage device 308 stores δ(N1) of Nn/N1 for l unit block.
is stored, so the ratios of all adjacent δ(N,), δp+, (N1)/δp(N,) and δp(Nl)/
δp+1(Nt) is checked for 1≦p<Nn/N1, and if even one exceeds a predetermined threshold Th, it is determined that a sudden change has been detected. Threshold T
h is determined by experience.

The explanation of the embodiments so far has been based on the assumption that the normalization circuit 2 exists, but as already mentioned in the explanation of the conventional ATC with reference to FIGS. 4 and 6, the input signal is The process of normalizing by variance can also be omitted. However, unlike the conventional example, the buffer cannot be omitted.

Note that in FIG. 1, when the input signal shown in FIG. 6 is not normalized, the storage device 26 and selector 29 are unnecessary.

(Effects of the Invention) As described in detail above, according to the present invention, the optimal block length is selected using the inter-block difference of transform coefficients obtained by performing linear transformation with different block lengths, and the optimal block length is supported. In order to transmit information by quantizing the transformed transform coefficients, an adaptive transform code is developed that can compress the amount of auxiliary information and improve the encoding quality while satisfying the conflicting demands of resolution and tracking changes in the properties of the input signal. A method and apparatus for oxidation can be provided.

[Brief explanation of drawings]

Figure 1 is a block diagram showing one embodiment of the present invention, Figure 2 is a diagram showing an example of the state of a buffer that stores input samples and the procedure for selecting the optimal block length, and Figure 3 is a difference between Figure 2. FIG. 4 is a block diagram showing the details of the detection circuit; FIG. 4 is a block diagram showing a conventional example; FIGS.
Fig. 6 shows another conventional example, and Fig. 7 (a), (b)
) is a diagram showing details of the normalization circuit and denormalization circuit in FIG. 6. In the figure, 1.17.301 is an input terminal, 2 is a normalization circuit, 3 is a linear conversion circuit, 4 is a quantizer, 6 is a bit allocation circuit, 8 is a transmission line, 15 is a multiplexing circuit, 25.26 ．．
3031, ..., 303n, 308.310.3
15 is a storage device, 27, 28, 29, 304, 313 is a selector, 36 is a difference detection circuit, 302 is a switch, 3
05 is a subtracter, 306 is a multiplier, 307 is an accumulator, 30
9 is a maximum value detection circuit, 316 is a divider, 311 is an optimal block length selection circuit, 312 is a sudden change detection circuit, 16.3
14 indicates output terminals, respectively.

Claims (2)

[Claims] (1) When adaptively converting an input signal to compress and transmit/storage the information content of a signal such as voice/music, if a block length is specified, the specified block length is used. Otherwise, the input signal samples are stored in a buffer, the linear transform is performed with a plurality of block lengths, and the obtained transform coefficients and auxiliary information are each independently stored, and at the same time Find the inter-block difference of the transform coefficients corresponding to the block length, and use the ratio of the inter-block difference corresponding to two adjacent block lengths when the plurality of block lengths are arranged in order of size and the inter-block difference. determine the optimal block length, select the stored transform coefficients and auxiliary information corresponding to the optimal block length, and quantize the selected transform coefficients by bit allocation calculated using the transform coefficients. and transmitting/storing the quantization output, bit allocation information, and the selected auxiliary information together with the optimum block length. (2) a buffer for accumulating input samples; a linear transformation circuit for performing linear transformation with a plurality of block lengths; a first storage device for storing the obtained transformation coefficients; and a first storage device for storing the obtained transformation coefficients; a second storage device that stores information; a difference detection circuit that receives the transform coefficients corresponding to a plurality of block lengths and outputs an optimal block length using inter-block differences in the transform coefficients; a first selector that receives an optimal block length to be processed and a block length designation signal supplied from the outside and selects an output according to the block length designation signal; a second selector that selects a value corresponding to the output of the first selector; a third selector that receives an output of the second storage device and selects a value that corresponds to the output of the first selector; a bit allocation circuit that calculates bit allocation for transform coefficients based on the output of a second selector; and quantization that quantizes the transform coefficients selected by the second selector according to the bit allocation obtained by the bit allocation circuit. a multiplexing circuit for multiplexing and transmitting/accumulating the output of the first selector, the output of the quantizer, the output of the bit allocation circuit, and the output of the third selector; The detection circuit includes a switch that switches input conversion coefficients according to a plurality of block lengths, a plurality of storage devices connected to the plurality of output terminals of the switch, and one of the outputs of the plurality of storage devices. a fourth selector for selecting, a subtracter for subtracting the output of the fourth selector from the input conversion coefficient, and a multiplier for squaring the output of the subtracter;
an accumulator that accumulates the output of the multiplier; a third storage device that stores the output of the accumulator; and a maximum value detection circuit that determines a maximum value from a plurality of outputs of the third storage device. , a fourth storage device that stores the output of the maximum value detection circuit, a divider that calculates a ratio of two data among the plurality of outputs of the fourth storage device, and stores the output of the divider. a fifth storage device; an optimal block length selection circuit that determines an optimal block length using the output of the fifth storage device; a sudden change detection circuit for detecting a significant change in the sudden change detection circuit; and a fifth circuit that selects and outputs either the output of the optimum block length selection circuit or the output of the sudden change detection circuit according to the output of the sudden change detection circuit. An adaptive transform encoding device comprising a selector.