JPH03174884A - Drive circuit for liquid crystal display device - Google Patents

Drive circuit for liquid crystal display device

Info

Publication number
JPH03174884A
JPH03174884A JP33847290A JP33847290A JPH03174884A JP H03174884 A JPH03174884 A JP H03174884A JP 33847290 A JP33847290 A JP 33847290A JP 33847290 A JP33847290 A JP 33847290A JP H03174884 A JPH03174884 A JP H03174884A
Authority
JP
Japan
Prior art keywords
liquid crystal
electrode
level
gate
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33847290A
Other languages
Japanese (ja)
Inventor
Susumu Ooima
大今 進
Yutaka Senoo
妹尾 豊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP33847290A priority Critical patent/JPH03174884A/en
Publication of JPH03174884A publication Critical patent/JPH03174884A/en
Pending legal-status Critical Current

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  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

PURPOSE:To prevent luminance change due to polarity inversion of a drive signal of a liquid crystal by driving the liquid crystal symmetrically with respect to an opposite electrode level vertically even when a gate-source capacitance of a thin film transistor(TFT) exists. CONSTITUTION:A bias power supply 8 is inserted between a reference level point and an opposite electrode 4. Thus, the ground level is decreased with respect to a drain reference level (0V) being a center level of a drain signal by an opposite electrode level VB, and even when the drain signal is decreased by V0 ( V0') at the OFF state of the TFT, the waveform symmetrical in the vertical direction with respect to the opposite electrode level is formed. Even with presence of the reduction in the level of an AC drive signal due to a capacitor in existence between the gate and the source of the TFT, no luminance change is caused at the polarity inversion of the drive signal of the liquid crystal.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、液晶TV等の液晶表示装置の駆動方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for driving a liquid crystal display device such as a liquid crystal TV.

(ロ)従来の技術 従来の液晶表示装置、例えば、「三洋テクニカルレビュ
J VOL16.NO,2’84(’) 23頁乃至2
8頁記載のアモルファスシリコンの薄膜トランジスタ(
TPT)を用いたアクティブマトリックス液晶表示(L
CD)パネルは、第4図に模式的に示す如く、T P 
T (1)のマトリックスアレイ及び表示電極(2)を
設けた表示電極基板(3)とこれに対向する対向電極(
4)を備えた対向電極基板(5)との間に液晶が充填さ
れている。尚、(G)、(D)、(S)は夫々TPT(
1)のゲート電極、ドレイン電極及びソース電極である
(b) Conventional technology Conventional liquid crystal display devices, for example, "Sanyo Technical Review J VOL 16. NO, 2'84 (') pp. 23-2
The amorphous silicon thin film transistor described on page 8 (
Active matrix liquid crystal display (L
CD) The panel is T P as schematically shown in Figure 4.
A display electrode substrate (3) provided with a matrix array of T (1) and a display electrode (2), and a counter electrode (
Liquid crystal is filled between the counter electrode substrate (5) and the counter electrode substrate (5). In addition, (G), (D), and (S) are respectively TPT (
These are the gate electrode, drain electrode, and source electrode of 1).

上述の液晶表示装置において、表示電極(2)と対向電
極(4)との間ではコンデンサが形成された溝底になっ
ており、例えば、液晶TVに用いた場合、ゲート信号源
からゲート電極(G)に所定の電圧が印加され、1水平
走査期間、導通状態となると、この間にドレイン信号源
からドレイン電極に印加されるドレイン電圧が前記コン
デンサに蓄積され、この電荷が、1垂直走査期間保持さ
れるようになっている。
In the above-mentioned liquid crystal display device, there is a groove bottom in which a capacitor is formed between the display electrode (2) and the counter electrode (4). For example, when used in a liquid crystal TV, the gate electrode ( When a predetermined voltage is applied to G) and it becomes conductive for one horizontal scanning period, the drain voltage applied from the drain signal source to the drain electrode during this period is accumulated in the capacitor, and this charge is retained for one vertical scanning period. It is now possible to do so.

上述の液晶表示装置においては、液晶を駆動する際、液
晶の耐久性を考慮して、通常、交流駆動するのが好まし
い。例えば、従来液晶TVの場合には1フイールド毎に
ドレイン信号の極性を基準レベル(対向電極レベル)を
中心に反転させるようにしている。
In the above-mentioned liquid crystal display device, when driving the liquid crystal, it is usually preferable to perform AC driving in consideration of the durability of the liquid crystal. For example, in the case of a conventional liquid crystal TV, the polarity of the drain signal is inverted about the reference level (counter electrode level) every field.

ここで、本願出願人は第4図のような1画素に対応する
等価回路を想定し、この等価回路に第5図に示すような
1画素にかかる疑似的な信号を印加して液晶の駆動電圧
を測定した。
Here, the applicant assumes an equivalent circuit corresponding to one pixel as shown in Fig. 4, and applies a pseudo signal for one pixel as shown in Fig. 5 to this equivalent circuit to drive the liquid crystal. The voltage was measured.

第4図において、CLは表示電極と対向電極間で形成さ
れる容量値と等価なダミーコンデンサ、CTはTPTの
ゲートとソース間に形成される容量、(6)はドレイン
信号源である。この等価回路に第5図に示すようなゲー
ト信号及びドレイン信号を印加した。ここで対向電極レ
ベルとドレイン信号の基準レベルは同一でともに接地電
位である。
In FIG. 4, CL is a dummy capacitor equivalent to the capacitance formed between the display electrode and the counter electrode, CT is the capacitance formed between the gate and source of TPT, and (6) is a drain signal source. A gate signal and a drain signal as shown in FIG. 5 were applied to this equivalent circuit. Here, the counter electrode level and the reference level of the drain signal are the same and both are at ground potential.

ゲート信号は1水平走査(IH)期間印加され、ゲート
電圧(V c、l)テT P T(1)7!l’オン、
(VGL)テオフとなる。また、ドレイン信号は基準レ
ベル(例えばOV)を中心にAフィールド時は電圧(v
Ill)、Bフィールド時は電圧(Vo)となるように
1フイールド毎に極性反転されている。
The gate signal is applied for one horizontal scanning (IH) period, and the gate voltage (V c, l) T P T (1) 7! l'on,
(VGL) Becomes Teoff. In addition, the drain signal is centered around the reference level (for example, OV), and during the A field, the voltage (v
During the B field, the polarity is inverted for each field so that the voltage (Vo) is obtained.

上述の信号が印加された状態でダミーコンデンサ(CL
)の両端の電圧を測定すると第6図に示す如く、Aフィ
ールドにおいてゲート信号によりlH期間、ダミーコン
デンサ(CL)に充電され、端子電圧(VcL)はVD
まで立ち上がるがゲート信号がvLとなると、前記端子
電圧(VcL)はVDから所定電圧v、と低下し、V 
cL= V CLI(= V o−V −)となり、以
降は次のゲート信号が印加・されるまで略その電圧を保
持する。
When the above signal is applied, the dummy capacitor (CL
), as shown in Figure 6, the dummy capacitor (CL) is charged by the gate signal in the A field for a period of 1H, and the terminal voltage (VcL) is VD.
However, when the gate signal becomes vL, the terminal voltage (VcL) decreases from VD to a predetermined voltage v, and V
cL=V CLI (=V o -V -), and thereafter approximately that voltage is maintained until the next gate signal is applied.

またBフィールドにおいては、ゲート信号により端子電
圧(VCL)は−Voまで立ち上がるが、ゲート信号が
■、となると、端子電圧(VCL)はさらにV1低下し
、VCL=VCL1(=  Vo  Vl)となる。
In addition, in the B field, the terminal voltage (VCL) rises to -Vo due to the gate signal, but when the gate signal becomes ■, the terminal voltage (VCL) further decreases by V1, and becomes VCL = VCL1 (= Vo Vl). .

上述のようにTPTがオンの間にダミーコンデンサ(C
L)への充電が充分であるにも拘わらず、TPTがオン
すると、端子電圧が低下する現象は第4図に示す容量(
Cア)のためと考えられる。
As mentioned above, the dummy capacitor (C
The phenomenon in which the terminal voltage decreases when the TPT is turned on even though there is sufficient charge to the capacitor (L) is shown in Figure 4.
This is thought to be due to C a).

すなわち、Aフィールドにおいて、T P T (11
がオン状態のとき、ソース電極(S)とドレイン電極(
D)とが接続され、ソース電極(S)に電圧VDが印加
され、ダミーコンデンサ(CL)が瞬時に充電される。
That is, in the A field, T P T (11
is in the on state, the source electrode (S) and the drain electrode (
D) is connected, voltage VD is applied to the source electrode (S), and the dummy capacitor (CL) is instantly charged.

更に、このとき、容量(C、T )にはVoよりも更に
高い■。がゲート電極(G)に印加されている。
Furthermore, at this time, the capacity (C, T) is even higher than Vo. is applied to the gate electrode (G).

次に、T P T (1)がオフ、すなわち、ソース電
極(S)とドレイン電極(D)が離間されるとともにゲ
ート電極(G)が正電圧のV。8から負電圧であるVG
Lに変化すると、ダミーコンデンサ(CL)の電荷の一
部が容量(Ct)(IIへ移動する。このためソース電
極(S)の電位がV、だけ低下する。(尚、ここで容量
(Cア)はダミーコンデンサ(CL)に比してその容量
値は充分小さいものと考えられる。)同様にBフィール
ドにおいて、T P T (1)がオンからオフになっ
たとき、ソース電極(S)の電位は−VDから更にv、
′だけ低下する。
Next, T P T (1) is turned off, that is, the source electrode (S) and drain electrode (D) are separated and the gate electrode (G) is at a positive voltage V. VG which is a negative voltage from 8
When the voltage changes to L, part of the charge in the dummy capacitor (CL) moves to the capacitor (Ct) (II. Therefore, the potential of the source electrode (S) decreases by V. (Here, the capacitor (C A) is considered to have a sufficiently small capacitance value compared to the dummy capacitor (CL).) Similarly, in field B, when T P T (1) changes from on to off, the source electrode (S) The potential of is further v from −VD,
′ decreases by .

上述の如く、T P T (1)のゲート、ソース間の
容量(Ct)の存在によって、微小ではあるが、ダミー
コンデンサ(CL)の端子電圧(VCL)すなわち液晶
の駆動電圧は、TPTがオフとなると、印加されたドレ
イン信号よりも所定量低下するため、対向電極レベルに
対して上下非対称となり液晶TVの場合、画像のコント
ラスト低下等の画質低下を引き起こす。尚、Aフィール
ド時及びBフィールド時で液晶の駆動電圧の低下、■、
及びvlはいずれも略等しい値であることも実験により
認められた。
As mentioned above, due to the existence of the capacitance (Ct) between the gate and source of TPT (1), the terminal voltage (VCL) of the dummy capacitor (CL), that is, the driving voltage of the liquid crystal, is slightly reduced when the TPT is turned off. In this case, since the voltage is lowered by a predetermined amount than the applied drain signal, it becomes vertically asymmetrical with respect to the level of the counter electrode, and in the case of a liquid crystal TV, this causes a reduction in image quality such as a reduction in image contrast. In addition, the drop in liquid crystal drive voltage during A field and B field,
It was also confirmed through experiments that both of and vl were approximately equal values.

(ハ〉発明が解決しようとする課題 本発明は、上述の従来の欠点に鑑みてなされたものであ
り、液晶の駆動信号の櫨性反転時に輝度変化が起こらな
い液晶表示装置の駆動方法を提供するものである。
(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned conventional drawbacks, and provides a method for driving a liquid crystal display device in which no change in brightness occurs when the liquid crystal drive signal is reversed. It is something to do.

(ニ)課題を解決するための手段 マトリクス配置された複数の表示電極のそれぞれに半導
体素子が結合された表示電極基板、該表示電極基板の各
表示電極に対向する対向電極を備えた対向を極基板、及
びこれら両基板間に充填された液晶物質を備えた液晶表
示装置の駆動回路において、 前記表示電極基板の半導体素子のゲート電極には接地電
位を基準としたゲート信号を供給するゲート信号源が接
続され、半導体素子のドレイン電極には接地電位を基準
とした交流のドレイン信号を供給するドレイン信号源が
接続され、更に半導体素子のソース電極には前記表示電
極が接続されてなり、前記対向電極基板の対向電極には
接地電位を基準としたバイアス電圧を供給するためのバ
イアス電源を接続するものである。
(d) Means for solving the problem A display electrode substrate in which a semiconductor element is bonded to each of a plurality of display electrodes arranged in a matrix, a counter electrode having a counter electrode facing each display electrode of the display electrode substrate; In a driving circuit for a liquid crystal display device including a substrate and a liquid crystal substance filled between these two substrates, a gate signal source supplies a gate signal based on a ground potential to a gate electrode of a semiconductor element of the display electrode substrate. is connected to the drain electrode of the semiconductor element, a drain signal source that supplies an alternating current drain signal with reference to ground potential is connected to the drain electrode of the semiconductor element, the display electrode is connected to the source electrode of the semiconductor element, and the opposing A bias power supply for supplying a bias voltage based on a ground potential is connected to the opposing electrode of the electrode substrate.

(ホ)作用 本発明によれば、TPTのゲート、ソース間に存在する
容量による交流駆動信号のレベル低下があっても、該交
流駆動信号は対向電極レベルに対して上下対称となる。
(E) Effect According to the present invention, even if the level of the AC drive signal is lowered due to the capacitance existing between the gate and source of the TPT, the AC drive signal becomes vertically symmetrical with respect to the level of the counter electrode.

(へ)実施例 以下図面に従い本発明の一実施例を説明する。(f) Example An embodiment of the present invention will be described below with reference to the drawings.

本実施例における液晶駆動回路の等価回路は第1図に示
す如く、基準電位点と対向電極(4)との間にバイアス
電源(8)を挿入している。尚、(7)はゲート信号源
である。これにより、第2図に示す如く、接地電位をド
レイン信号の中心電位としたドレイン基準レベル(OV
)に対して、対向電極レベルは■3だけ低下することに
なり、前述の如くドレイン信号がTPTオフ時にV o
 (#V o ’ )だけ低下しても、対向電極レベル
に対しては上下対称の波形となる。ここで、■、はV、
と等しくなるよう設定する。尚、交流駆動させた対極レ
ベル及びドレイン信号の極性をIH毎に反転させて駆動
した場合も本発明を応用することも可能である。
As shown in FIG. 1, the equivalent circuit of the liquid crystal drive circuit in this embodiment has a bias power supply (8) inserted between the reference potential point and the counter electrode (4). Note that (7) is a gate signal source. As a result, as shown in Fig. 2, the drain reference level (OV
), the counter electrode level decreases by ■3, and as mentioned above, when the drain signal is V o
Even if the voltage decreases by (#V o '), the waveform becomes vertically symmetrical with respect to the counter electrode level. Here, ■ is V,
Set it to be equal to . The present invention can also be applied to the case where the counter electrode level and the polarity of the drain signal driven by AC are reversed for each IH.

また、安定した表示を得るために画素容量と並列に補助
容量を形成する場合にも本発明は有効である。
The present invention is also effective when an auxiliary capacitor is formed in parallel with the pixel capacitor in order to obtain stable display.

(ト)発明の効果 本発明によれば、交流駆動信号の基準レベルと対向電極
間に所定のバイアス電圧を印加することにより、液晶を
交流駆動するTFTLCDパネルにおいて、TPTのゲ
ート、ソース間の容量が存在しても、液晶が対向電極レ
ベルに対して上下対称となるように駆動できるため、例
えば液晶TVの場合、1フイールドことの極性反転によ
る輝度変化がなく、コントラスト等の画質低下を招くこ
とがない。
(G) Effects of the Invention According to the present invention, the capacitance between the gate and the source of TPT is achieved in a TFTLCD panel in which the liquid crystal is AC driven by applying a predetermined bias voltage between the reference level of the AC drive signal and the opposing electrode. Even if there is, the liquid crystal can be driven vertically symmetrically with respect to the counter electrode level, so in the case of a liquid crystal TV, for example, there is no brightness change due to polarity reversal for one field, which causes a decline in image quality such as contrast. There is no.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の液晶駆動回路の等価回路図
、第2図は第1図の本発明の一実施例の動作図、第3図
は従来のTPTアクティブマドノックスパネルの模式図
、第4図は従来のTPTアクティブマトリックスパネル
の等価回路図、第5図は本発明の駆動波形図、第6図は
ダミーコンデンサの端子電圧波形図である。 (1)・・TPT、(2)  ・表示電極、(3)・・
・表示電極基板、(4)・・対向を極、(5)・・対向
電極基板、(6)・・ドレイン信号の信号源、(7)・
・ゲート信号の信号源、 (8)・・・バイアス電源。
Fig. 1 is an equivalent circuit diagram of a liquid crystal drive circuit according to an embodiment of the present invention, Fig. 2 is an operational diagram of an embodiment of the present invention shown in Fig. 1, and Fig. 3 is a schematic diagram of a conventional TPT active Madnox panel. 4 is an equivalent circuit diagram of a conventional TPT active matrix panel, FIG. 5 is a drive waveform diagram of the present invention, and FIG. 6 is a terminal voltage waveform diagram of a dummy capacitor. (1)... TPT, (2) ・Display electrode, (3)...
・Display electrode substrate, (4)...Opposing pole, (5)...Counter electrode substrate, (6)...Drain signal source, (7)...
・Signal source of gate signal, (8)...Bias power supply.

Claims (1)

【特許請求の範囲】[Claims] (1)マトリクス配置された複数の表示電極のそれぞれ
に半導体素子が結合された表示電極基板、該表示電極基
板の各表示電極に対向する対向電極を備えた対向電極基
板、及びこれら両基板間に充填された液晶物質を備えた
液晶表示装置の駆動回路において、 前記表示電極基板の半導体素子のゲート電極には接地電
位を基準としたゲート信号を供給するゲート信号源が接
続され、半導体素子のドレイン電極には接地電位を基準
とした交流のドレイン信号を供給するドレイン信号源が
接続され、更に半導体素子のソース電極には前記表示電
極が接続されてなり、前記対向電極基板の対向電極には
接地電位を基準としたバイアス電圧を供給するためのバ
イアス電源が接続されたことを特徴とする液晶表示装置
の駆動回路。
(1) A display electrode substrate in which a semiconductor element is bonded to each of a plurality of display electrodes arranged in a matrix, a counter electrode substrate provided with a counter electrode facing each display electrode of the display electrode substrate, and a space between these two substrates. In a driving circuit for a liquid crystal display device including a filled liquid crystal material, a gate signal source that supplies a gate signal with reference to a ground potential is connected to the gate electrode of the semiconductor element of the display electrode substrate, and the drain of the semiconductor element is connected to the gate electrode of the semiconductor element of the display electrode substrate. A drain signal source that supplies an alternating current drain signal with reference to ground potential is connected to the electrode, the display electrode is connected to the source electrode of the semiconductor element, and the counter electrode of the counter electrode substrate is connected to the ground. A driving circuit for a liquid crystal display device, characterized in that a bias power supply for supplying a bias voltage based on a potential is connected.
JP33847290A 1990-11-30 1990-11-30 Drive circuit for liquid crystal display device Pending JPH03174884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33847290A JPH03174884A (en) 1990-11-30 1990-11-30 Drive circuit for liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33847290A JPH03174884A (en) 1990-11-30 1990-11-30 Drive circuit for liquid crystal display device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP23710484A Division JPS61116392A (en) 1984-11-09 1984-11-09 Driving of liquid crystal desplay unit

Publications (1)

Publication Number Publication Date
JPH03174884A true JPH03174884A (en) 1991-07-30

Family

ID=18318483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33847290A Pending JPH03174884A (en) 1990-11-30 1990-11-30 Drive circuit for liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH03174884A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457474A (en) * 1993-11-11 1995-10-10 Nec Corporation Driving circuit for active-matrix type liquid crystal display

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54106194A (en) * 1978-02-08 1979-08-20 Sharp Corp Driving method for matrix type liquid crystal display unit
JPS58173794A (en) * 1982-04-06 1983-10-12 セイコーエプソン株式会社 Driving of matrix type liquid crystal display unit
JPS59119328A (en) * 1982-12-27 1984-07-10 Fujitsu Ltd Driving method of liquid crystal display panel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54106194A (en) * 1978-02-08 1979-08-20 Sharp Corp Driving method for matrix type liquid crystal display unit
JPS58173794A (en) * 1982-04-06 1983-10-12 セイコーエプソン株式会社 Driving of matrix type liquid crystal display unit
JPS59119328A (en) * 1982-12-27 1984-07-10 Fujitsu Ltd Driving method of liquid crystal display panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457474A (en) * 1993-11-11 1995-10-10 Nec Corporation Driving circuit for active-matrix type liquid crystal display

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