JPH03174000A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten operation time by varying the mutual conductance of two elements constituting a memory cell for one bit in an erasing state or varying the channel width and length of FET constituting the two elements in a non-volatile semiconductor memory device using a differential amplification type sense amplifier. CONSTITUTION:In an EPROM accelerating the access speed by using a differential amplification type sense amplifier 5, a memory cell 1 is constituted so that the mutual conductance of one FAMOSQ 1 can be larger than that of another FAMOSQ 2 in the erasing state. Thus, it is enough to process the write of the Q1 only to the information memory of logic 0 and it is not necessary to turn any one of the MOS to a write state without fail in respect to the information memories of logic 1 and 0. Then, the program time of the EPROM is shortened. Namely, memory capacity is made double in respect to the ROM of conventional structure for which it is necessary to make the structure and characteristic of the element same and to write one of the MOS without fail for determining the logic 1 or 0.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically writable nonvolatile semiconductor memory device, for example, two electrically writable nonvolatile semiconductor memory devices connected to respective complementary bit lines. An ultraviolet erasing type EPR in which a 1-bit memory cell is configured with a digital memory element and a differential amplification type sense amplifier detects the logical value of read data.
This invention relates to technology that is effective when applied to OM (Electrically Programmable Read Only Memory).

[Conventional technology]

From the viewpoint of high-speed access to non-volatile semiconductor memory devices, an ultraviolet erase type EPROM using two electrically writable transistors such as FAMO3 (floating gate avalanche injection insulated gate field effect transistor) has been proposed. ing. Such an EPROM is, for example, manufactured by the Institute of Electrical Communication Engineers SDM89
-16 (March 1989), pages 43 to 45, “16
nS 64 bit CMO3EPROMJ and two FAMs connected to each of the complementary bit lines.
O5 constitutes a memory cell for the pit, and the logical value of read data is detected by a differential amplification type sense amplifier. At this time, the FAMO 3 provided oppositely to each memory cell is the same, and the logic 1 or logic 0 of data stored in each memory cell is determined depending on which FAMO 8 is being written. That is,
As shown in FIG. 3A, FAMO8Qjt coupled to complementary bit line BLi is put into the erased state and BU
Assuming that the stored data is a logic 1 when FAMOS Qjb coupled to i is in the write state, to store a logic O, the FAMOS Qjb coupled to complementary bit line BLi should be FAMO3Qjt is put into write state and FAMO3Qj is coupled to BLi.
b is put into the erased state. When a memory cell storing a logic 1 is selected by the word line WLi, the current becomes ≠O9 current 2=O as shown in FIG. By being detected by the dynamic amplification type sense amplifier 5, the logic value 1 of the data is determined. Furthermore, when a memory cell storing a logic O is selected by the word aWLi, the current 11=O and the current I2≠O as shown in FIG. By being detected by the dynamic amplification type sense amplifier 5, the logical value O of the data is determined.

[Problem to be solved by the invention]

However, as in the prior art, non-volatile memory elements such as FAMO3 arranged oppositely to constitute one memory cell are the same in structure and characteristics, and the logic level of data stored in each memory cell is 1. The inventor discovered that in order to determine the logical O, it is necessary to write to one of the FAMO8s, and that there is a problem in that when the memory capacity is large, the program operation takes a significant amount of time. Ta.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device in which a program operation time for memory cells can be shortened in a structure using a differential amplification type sense amplifier. Another object of the present invention is to shorten the programming time for a nonvolatile semiconductor memory device that configures memory cells for ↓ pits by two electrically writable nonvolatile memory elements connected to complementary bit lines. This is what we are trying to do.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

(Means for Solving Problem i) A brief overview of typical inventions disclosed in this application is as follows.

In other words, a 1-bit memory cell is formed by two electrically writable nonvolatile memory elements connected to complementary bit lines, and a nonvolatile memory cell in which the logical value of read data is detected by a differential amplification type sense amplifier. In a semiconductor memory device, mutual conductance of two nonvolatile memory elements constituting a memory cell for one bit is made different in an erased state, or two nonvolatile memory elements constituting a memory cell for one bit are configured. The channel width or channel length of the field effect transistors to be used is different.

When a memory cell is composed of ■ nonvolatile storage elements and a differential amplification type sense amplifier is used, the current is formed by the current of a transistor whose mutual conductance is smaller than the mutual conductance of the nonvolatile storage element in the erased state. It employs a differential amplification type sense amplifier that detects the logical value of read data by comparing a reference level with a read level from a memory cell.

[For production]

According to the above-mentioned means, when both nonvolatile memory elements arranged opposite to each other in memory cells corresponding to t pits are kept in an erased state, the difference in mutual conductance or the difference in channel width or channel length between the nonvolatile memory elements is achieved. Accordingly, a difference occurs in the current flowing through the memory element to the complementary bit line.

That is, a larger current flows through the nonvolatile memory element having relatively larger mutual conductance, shorter channel length, or wider channel width. As a result, the complementary levels appearing on the complementary bit lines are amplified by the differential amplification type sense amplifier, thereby determining the logical value of the memory cell data at that time. When inverting the logical value of the memory cell data, it is sufficient to put the nonvolatile memory element with relatively larger mutual conductance, shorter channel length, or wider channel width into the write state. As a result, the non-volatile storage element that has been put into the write state is cut off, and the current flowing through the non-volatile storage element on the opposite side is now increased, thereby increasing the complementary level reversed from the above. A differential amplification type sense amplifier amplifies the data, thereby determining the logical value of the memory cell data.

When a memory cell is configured with one non-volatile memory element and a differential amplification type sense amplifier is used, the transistor forming the reference level of the differential amplification type sense amplifier has a mutual conductance of the two-transistor type memory cell. It acts similarly to the smaller non-volatile storage element.

〔Example〕

FIG. 1 shows an EPROM according to an embodiment of the present invention. The EPROM shown in the figure is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

Although not particularly limited, the EPROM of this embodiment is a FAM as an electrically writable nonvolatile semiconductor memory element.
One memory cell 1 is configured using two O3QI and Q2, and left and right FAMO8TQ included in each memory cell 1
The drains of I and Q2 are connected to complementary bit lines BL, BL for each column.
,” BLn, coupled to BLn, and each FAMO8Q
The control gates of I and Q2 are connected to the word lines WL and Q2 for each row.
~bound to WLn. Here is FAMO8QI.

Writing data to Q2 is performed by applying a write voltage higher than the voltage of the read system between the word line and the bit line, and injecting hot electrons generated near the drain region of the channel portion into the floating gate. Further, erasing is performed by ultraviolet irradiation.

A predetermined one of the word lines WL and WLn is driven to a selection level according to the output of the row address decoder and driver 2. This selection operation is performed by a row address signal AD supplied from the outside via an address buffer (not shown).
Follow Rr. In a data read operation, a predetermined word line selected by a row address signal ADRr is moved by a read system voltage, for example, a power supply voltage of 5. When a write operation is instructed, the row address signal AD
A write high voltage, such as 12V, is applied to a predetermined word line selected by Rr.

The complementary bit line B L (I HB Lo-B L n
, B Ln is column selection switch MO3FETQ
C.

QC, "QCn, complementary common data line C via QCn
Commonly connected to D and CD. Column selection switch MO3
A predetermined one of the FETs QC, , QC, -QCn, QCn is selected according to the output of the column address decoder 3.

This selection operation follows a column address signal ADRc supplied from the outside via an address buffer (not shown).

The common data lines CD and CD are connected to an N-channel MO8FETQ3 which is pulled up to the power supply terminal vCC.
and a precharge circuit constituted by an inverter 4, a pair of input terminals of a differential amplification type sense amplifier 5 are coupled, and an output terminal of a write circuit 6 is connected to one non-inverting common data line CD. combined.

Here, the non-inverted bit lines BL, which are commonly connected to one non-inverted common data line CD, are FAMO3QI on the BLn side.
The mutual conductance (gm) in the erased state is relatively larger than that of FAMO3Q2 on the opposite side. In the memory cell 1 having this structure, for example, information storage of logic 1 is performed by setting both FAMOs 5QI and Q2 to an erased state. Furthermore, information storage of logic O is obtained by writing only to FAMO8Q1, which has a relatively large mutual conductance.

FIG. 2A schematically shows the read operation state of a memory cell storing a logic 1. In this state, both FAMO3QIs are in the erased state.

When Q2 is selected by word line WLi, both F
AMO8QI, current I0. flowing through Q2. I.

Both take the relationship L>I2, not O. As a result, the complementary levels appearing on the complementary bit lines B L , ) r B L J are detected by the differential amplification type sense amplifier S, thereby determining whether the read data is logic 1.

FIG. 2B schematically shows the read operation state of a memory cell storing a logic O. In this state, only one FAMO8QI whose mutual conductance is relatively large is in the write state.

Therefore, FAMO3Q included in this memory cell 1
When I and Q2 are selected by the word line WLi, the current I=0. The current flow 2≠O, and as a result, a complementary level reversed from the above appears on the complementary bit lines BLj, BLj, and this is amplified by the differential amplification type sense amplifier 5, so that the logic O of the read data is It will be judged.

FAMO3Q1, Q2 in such memory cell 1
The mutual contactance of the channels can be varied by controlling the channel width or channel length. For example, to make the channel lengths different, the ratio W/L of the channel width W to the channel length should be set to 1.210.8 for FAMOSQ1 with large mutual conductance, and W/L should be set to 1.210.8 for the other FAMOSQ2. 1.2/
1.2. In addition, in order to make the channel width different, it is necessary to use an FA with large mutual conductance.
For MO8QI, the ratio W/L of channel width W to channel length is 2. Olo, 8 and the other FAM
For O5Q2, it can be configured as W/Lti-1,210,8.

According to the above embodiment, there are the following effects.

(1) In an EPROM whose access speed is increased using a differential amplification type sense amplifier 5, the mutual conductance of one FAMO3QI is the same as that of the other FAMO3QI in the erased state.
By configuring the memory cell 1 to be larger than MO5Q2, for example, it is only necessary to write to FAMOS Q1 for information storage of logic O, and it is necessary to write to FAMOS Q1 for both information storage of logic 1 and logic O. Either F
There is no need to put AMOS into the write state, which allows
The programming time of EPROM can be shortened.

(2) From the above effects, the nonvolatile memory elements such as FAMO8 arranged oppositely to constitute one memory cell are assumed to be the same in structure and characteristics, and the data stored in each memory cell is Compared to EPROMs with a conventional structure in which writing must be done to one of the FAMO8 to determine logic 1 or logic O, the time required to program data is twice as long as the storage capacity. It is possible to make them almost the same even if they are different.

[Embodiment 2] FIG. 4 shows a portion of an EPROM according to another embodiment of the present invention. This EPROM has one memory cell 10.
The structure is made up of FAMO5QI and uses a differential amplification type sense amplifier 5.

At this time, the differential amplification type sense amplifier 11 is
The reference level formed by the current flowing through MOSFET Q4, which has a transconductance smaller than the transconductance in the erased state of O8QI, and memory cell 1
The logic value of the read data is determined by comparing the read level input from 0 through the common data line CD. In such a configuration, the MO5FETQ
4 functionally corresponds to FAMO8Q2 in FIG. Therefore, if it is made to correspond to the EPROM of FIG.

For example, when storing logic 1 information in the memory cell 10, FAMOS Q1 may be set to an erased state, and when storing logic 0 information, writing may be performed to FAMO8Q1. As a result, as in the embodiment shown in FIG. 1, in an EPROM in which the access speed is increased using the differential amplification type sense amplifier 1, it is only necessary to write the FAMO3QI to, for example, information storage of logic 0. Thereby, the programming time of the EPROM can be shortened.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, the EPROM of the above embodiment is configured such that data is read and written in units of l pi.
The present invention can also be applied to a circuit type in which a data latch circuit is provided on a bit line and data can be written in units of bytes at once. Further, the precharge format may be dynamic control using a timing signal.

In the above description, the invention made by the present inventor was mainly applied to EPROM, which is the background field of application, but the present invention is not limited thereto, and the present invention is not limited to this.・Erasable and programmable read only.

memory), and EPROM and EEPROM.

Alternatively, it can be widely applied to various semiconductor integrated circuits such as microcomputers that incorporate the memory element. The present invention can be applied to conditions where data is read from an electrically writable nonvolatile memory element using at least a differential amplification type sense amplifier.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, in a non-volatile semiconductor memory device using a differential amplification type sense amplifier, the mutual conductance of two non-volatile memory elements constituting a memory cell for 1 pit is made different in the erased state, or By making the channel widths or channel lengths of the field-effect transistors that make up the two nonvolatile memory elements that make up the cell different, it is possible to shorten the programming time for the memory cell without sacrificing high-speed access. effective.

When a memory cell is configured with one nonvolatile storage element and a differential amplification type sense amplifier is used, the current is formed by the current of a transistor whose mutual conductance is smaller than the mutual conductance of the nonvolatile storage element in the erased state. The same effect as described above can also be obtained by employing a differential amplification type sense amplifier that detects the logical value of read data by comparing the reference level and the read level from the memory cell. This can be distantly related to a decrease in the number of memory cell transistors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an EPROM according to an embodiment of the present invention, and FIGS. 2A and 2B are diagrams showing the case where memory cell data of logic ↓ and memory cell data of logic 0 are read in the EPROM of the construction drawing. FIGS. 3A and 3B are explanatory diagrams of operating states when reading logic 1 memory cell data and logic O memory cell data in a conventional EPROM, and FIG. EPROM according to the embodiment
FIG. 1...Memory cell, Ql, Q2...FAMO8,B
L,,BL,=BLn,BLn-complementary bit line, WL0
~WLn... Word line, CD, CD... Complementary common data line, 2... Row address decoder and driver, 3... Column address decoder, 5... Differential amplification type sense amplifier, 6... ...Write circuit, 10...Memory cell, 11...Differential amplification type sense amplifier, Q4...
・MOSFET.

Claims (1)

[Claims] 1. A 1-bit memory cell is configured by two electrically writable nonvolatile memory elements connected to each complementary bit line, and the logical value of read data is differentially amplified. A non-volatile semiconductor memory device that detects a type of sense amplifier using a type sense amplifier, characterized in that two non-volatile memory elements constituting the one-bit memory cell have mutual conductances different in an erased state. Device. 2. A 1-bit memory cell is configured by two electrically writable nonvolatile memory elements connected to each complementary bit line, and a differential amplification type sense amplifier detects the logical value of the read data. A nonvolatile semiconductor memory device, characterized in that the channel widths or channel lengths of field effect transistors forming two nonvolatile storage elements forming the 1-bit memory cell are different. Device. 3. A memory cell for one bit is formed by one electrically writable non-volatile memory element, and is formed by the current of a transistor whose mutual conductance is smaller than the mutual conductance of the non-volatile memory element in the erased state. A nonvolatile semiconductor memory device including a differential amplification type sense amplifier that compares a reference level with a read level from a memory cell to detect a logical value of read data.