JPH03171755A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce leak current within an element when it is biased inversely at a high temperature while maintaining a high isolation capability between elements through dielectric isolation by introducing a semiconductor layer with an opposite conductive type to that of an element region which is in contact with the dielectric between the element region and the dielectrically isolated region. CONSTITUTION:A structure with a semiconductor layer 205 having an inverse conductive type as an element region is formed between the N-type element region and a dielectric isolation region 203. By using a wafer which is in a structure where the periphery of these N-type element regions is surrounded by a P-type layer and by normal process, a base and an emitter are diffused and a transistor is formed at this element region. In this transistor, leak current between a base and a collector becomes approximately 1/50 as compared with the case when the element is formed in direct contact with SiO2 at 300 deg.C. Also, when the element region and the surrounding layer are inversely biased, leak current between the base and the collector can be reduced to approximately 1/100 as compared with the case when the element is formed in direct contact with the SiO2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a novel semiconductor device, and more particularly to a semiconductor device such as a bipolar IC in which at least some of its constituent elements are separated by a dielectric. This article relates to a structure that improves the characteristics of semiconductor devices at high temperatures. (Conventional technique) Generally, when separating each element in a bipolar IC, etc., an N-type element region is separated from a P-type substrate and a P-type substrate.
Surrounded by a type separation diffusion layer. PN junction isolation is used to reverse bias the PN junction formed here. This method is widely used because the manufacturing process is simple and it has sufficient element isolation capability in a normal IC usage environment. but,
High temperatures over 200℃ and radiation exposure. In environments where light irradiation is performed. The reverse leakage current of the PN junction increases, making it impossible to maintain sufficient element isolation capability. Also.
As methods other than PN junction isolation, mainly high withstand voltage,
A dielectric isolation method in which the element region is surrounded by a dielectric material such as Sint is used as an isolation method for manufacturing elements with high temperature resistance and radiation resistance, and for integrating light-receiving elements such as photodiodes. In this isolation method using a dielectric, the leakage current to the separation layer is greatly reduced compared to the method using PN junction isolation, but carriers generated at the interface between the dielectric and the element, especially when the temperature is raised, are This is because the minority carriers that are generated diffuse only to the junctions within the device. When the junction within the device is reverse biased, such as the base-collector junction of a transistor. There was a problem that the reverse leakage current of this junction became large. (Problems to be Solved by the Invention) The present invention has been made against the background of the above-mentioned problems of the prior art. The purpose is to reduce leakage current in biased junctions. (Means for Solving the Problems) The present invention provides a semiconductor device in which elements are isolated by m-electric isolation, in which a layer having a conductivity type opposite to that of the element layer is formed between a conventional element layer and a dielectric isolation layer. By interposing a semiconductor region, a semiconductor device is provided in which reverse leakage current at junctions within the component elements is reduced at high temperatures. this is,
Since most of the reverse leakage current of a junction at high temperatures is the diffusion current of minority carriers, the principle is that if a junction is placed nearby, the reverse leakage current of the other junction can be reduced depending on the bias conditions of the junction. This is due to
This MjI. This will be explained below using the analysis results of the general minority carrier diffusion equation (1) in a PN junction. d'Pn Pn-PnQ dx' τ p where op and τP are the diffusion coefficient and lifetime of minority carriers in the Nl layer, respectively. Figure 1 shows the reverse biased PINI junction on the Nl layer side. The thickness of the Nl layer is set to be less than the minority carrier diffusion length <P2.
Add a layer and reverse bias the resulting NIP2 junction (curve 1). N1 when set to lm emission (same n)
This is the concentration distribution of minority carriers in the layer. In addition, the dashed line (II
1) shows the concentration distribution of minority carriers that occurs under the expansion of the surface-generated current when the Nl layer is formed in contact with the directly sandwiched dielectric. By the way, it is well known that the diffusion current is proportional to the concentration gradient of minority carriers at the point W=O. Therefore, from Figure 1, by forming a P2 layer with a conductivity type opposite to that of the Ni layer between the Nl layer and the dielectric layer, the diffusion current to the PIN+ junction is reduced, and by reverse biasing the NIP2 junction, It can be seen that the diffusion current decreases significantly. In Figure 1, the thickness of the Ni layer is set to 1/Losi degrees of the minority carrier diffusion length, but it can be easily concluded from the analytical results that this effect becomes larger as the thickness of the Nl layer becomes smaller than the diffusion length. By the way. The present invention will be specifically explained below with reference to Examples. (Example) A 3-inch Nil silicon wafer with a resistivity of about IQcm, a (100) orientation, and a thickness of about 380 μm was used as the substrate. Thermal diffusion of boron was performed on the surface of this substrate to form a P-type layer of approximately 1 μm. Afterwards, this wafer was oxidized to form an oxide film of approximately 5,000 layers. Separately, we prepared a 3-inch wafer with approximately 5,000 oxide films formed on it. These two wafers were stacked and bonded together by heat treatment, and the N-type substrate was polished from the back side so that the thickness of the N-type single crystal layer was approximately 5 μm. Next, this wafer was oxidized, a pattern for isolation between elements was formed using photolithography, and using this oxidation pattern as a mask, etching was performed with an anisotropic etching solution to form isolation grooves. ．． and,
After thermally diffusing boron into the groove to form a P-type layer, the wafer was oxidized to form an oxidized layer on the surface of the groove. Furthermore, polycrystalline silicon was deposited on this wafer, and the surface was then polished to planarize it. In this way, in the dielectric isolation structure, there is a gap between the element region and the dielectric isolation waste. A structure with a semiconductor layer having a conductivity type opposite to that of the fR region was obtained. Using the wafer thus obtained, which has a structure in which the N-type device region is surrounded by a P-type layer, the base and emitter are diffused using a normal process to form a transistor in this device region. did. Figure 2 shows the structure of this transistor. This transistor has a base-collector leakage current of approximately 1750 at 300°C compared to the case where the element is made in direct contact with SiO2, and the element region and surrounding layers are reverse-biased. In this case, the pace-collector leakage current was reduced to about 17,400 compared to the case where the element was in direct contact with S10t. Although the embodiment of the present invention has been described above, in addition to this embodiment,
It goes without saying that the structure of the present invention can be made using the conventional method of making an IC with an M-electrode split structure. In addition, as a method for creating a diffusion layer in contact with the dielectric separator, we have also considered a method in which impurities that can obtain the desired diffusion layer are included in the dielectric, and the desired diffusion M is created during subsequent heat treatment. It will be done. (Effects of the Invention) According to the present invention, transistors, diodes, etc. can be separated by dielectrics. The parasitic volume of each cord was reduced, and the frequency characteristics were improved. Furthermore, even when the ambient temperature rose, the leakage current between the elements did not increase, and good A characteristics were obtained.

[Brief explanation of the drawing]

Figure 1 explains the principle of the present invention. The concentration of NIW is set to IXIO'%/3. Set the minority carrier diffusion length to 10
0μm. When the thickness of the Nl layer is 10 μm, Nl
The distribution of minority carriers in the layer is expressed as follows: when the NIP2 junction is reverse biased (I), when it is open (n),
and the case where the Nl layer is in direct contact with the dielectric material (■).

Claims (1)

[Claims] In a semiconductor device in which at least a part of the constituent elements is dielectrically isolated, a semiconductor layer having a conductivity type opposite to that of the element region in contact with the dielectric is interposed between the element region and the dielectric isolation region. A semiconductor device characterized by: