JPH03161937A - Manufacture of field-effect type transistor - Google Patents
Manufacture of field-effect type transistorInfo
- Publication number
- JPH03161937A JPH03161937A JP30245289A JP30245289A JPH03161937A JP H03161937 A JPH03161937 A JP H03161937A JP 30245289 A JP30245289 A JP 30245289A JP 30245289 A JP30245289 A JP 30245289A JP H03161937 A JPH03161937 A JP H03161937A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- electrode
- deposited
- manner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 230000008021 deposition Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 240000008168 Ficus benjamina Species 0.000 description 1
- 229930194542 Keto Natural products 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 125000000468 ketone group Chemical group 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、オフセット形のゲート電極を有した電界効果
形トランジスタの製遣方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor having an offset gate electrode.
電界効果形トランジスタとして、M E S F E
T(Metal ScmecondueLor Fie
ld Er[’cctTrans]stor)やM O
S F E T (Metal OxideScmc
conductor Field Efrcct Tr
ansistor )等が知られている。これらの電界
効果形トランジスタは、ソース電極が形成されるソース
領域とドレイン電極か形戊されるドレイン領域とを有し
、ソース領域とドレイン領域の相互間に位置するチャネ
ル層にゲート電極を形成して構成されており、これらの
中には、ゲート電極がソース領域とドレイン領域の相互
間の中央部からソース領域側へオフセットして形威され
たオフセットゲート形のものが存在する。As a field effect transistor, M E S F E
T(Metal ScmecondueLor Fie
ld Er['cctTrans]stor) and M O
S F E T (Metal Oxide Scmc
conductor Field Efrcct Tr
Ansistor) etc. are known. These field effect transistors have a source region in which a source electrode is formed and a drain region in which a drain electrode is formed, and a gate electrode is formed in a channel layer located between the source region and the drain region. Among these, there is an offset gate type in which the gate electrode is offset from the center between the source region and the drain region toward the source region.
このようにソース領域とドレイン領域の相互間の中央部
からオフセットして形成されるケー1・電極は、これま
では非自己整会型であった。また、半導体基板上に形威
されたゲート電極及びその側壁をマスクとして用い、不
純物イオンを半導体基板に注入してソース領域およびト
レイン領域を形成する場合には、ケート電極の側壁か通
常左右χ・l称でその側壁長か等しいことからオフセッ
ト形のケート電極を175ることはできなかった。The electrode formed offset from the center between the source region and the drain region in this way has hitherto been of a non-self-aligned type. Furthermore, when forming a source region and a train region by implanting impurity ions into the semiconductor substrate using a gate electrode formed on a semiconductor substrate and its sidewalls as a mask, the sidewalls of the gate electrode are usually It was not possible to use an offset type gate electrode because the lengths of the side walls were equal.
そこで、上述の事情に鑑み、本発明はオフセット描造を
右ずる′屯界効果形1・ランシスタを自己整合的に形成
することかできる電界効果形トランジスタの製造方法を
堤供することを11的としている。Therefore, in view of the above-mentioned circumstances, the present invention has an eleventh object to provide a method for manufacturing a field effect transistor that can form a field effect type transistor in a self-aligned manner with an offset pattern. There is.
上述の目的を達戊するため、本発明による電界効東形l
・ランジスタの製込方法においては、ゲート電極が形威
された基板表面に対して傾斜した方向から指向的にゲー
1・電極の片側側面を除いて第1絶縁膜を堆積させる工
程と、ゲート電極の側部に堆積した部分を残して業1絶
縁膜を旦板表面に対して垂直に異h゛的に除去する工程
と、L(板表面に対して無指向的に第2絶縁膜を推積さ
せる工程と、ゲート電極の側部に堆積した部分を残して
第2絶縁膜を乱板表面に対して乗直にシ゛4方的に除夫
ずる工程とを備えたことを特徴としている。In order to achieve the above-mentioned object, a field effect east type l according to the present invention is provided.
・The transistor manufacturing method includes a step of depositing a first insulating film directionally from a direction oblique to the substrate surface on which the gate electrode is formed, except for one side of the gate electrode; A process of firstly removing the first insulating film in an irregular manner perpendicular to the plate surface while leaving a portion deposited on the sides of the plate; The method is characterized by comprising a step of depositing the second insulating film, and a step of removing the second insulating film in a four-directional manner perpendicularly to the surface of the plate, leaving the deposited portion on the side of the gate electrode.
このようにすることにより、ゲー1・電極の両側部にr
zいに側壁長の異なる側壁か形成される。By doing this, r
z Side walls with different side wall lengths are formed.
以下、本発明の丈胞1列について第1図を参照しつつ、
説明する。Hereinafter, with reference to FIG. 1 regarding one row of long follicles of the present invention,
explain.
拍]園は本発明による’il5, W効果形1・ランジ
スタの製造方法をMESFETの製造に適用した場合の
工程図である。Figure 3 is a process diagram when the method for manufacturing a transistor of the W effect type 1 according to the present invention is applied to manufacturing a MESFET.
まず、同図(a)に示したように、半導体裁板1の表血
上にリフ1・オフ等によりゲー+− ′ili極2を直
接パターン形成する。ケー1・電地2は例えばタングス
テンW等の金屈て形威される。次に、半導体払板]の表
面に対して傾斜した方向から堆積方向に指向性を6゛ず
るECR−CVD法により第1絶縁膜3を■{“枯させ
る(同図(b)参照)。このとぎ、第1絶縁膜3は越板
表面に対して傾斜した方向から指向的に堆私するので、
ゲー1・電極2の影となる片側側面には坩゛積しない。First, as shown in FIG. 5A, a pattern of the gate electrode 2 is directly formed on the surface of the semiconductor cutting board 1 by riff 1 off or the like. The cable 1 and the electrical base 2 are made of metal such as tungsten W, for example. Next, the first insulating film 3 is dried by an ECR-CVD method in which the directivity is shifted by 6 degrees in the deposition direction from the direction inclined with respect to the surface of the semiconductor substrate (see FIG. 3(b)). At this point, the first insulating film 3 is deposited directionally from the direction inclined to the surface of the overboard.
Do not deposit on one side that will be in the shadow of Gate 1 and Electrode 2.
したがって、この部分を除いて半導体基板1およびゲー
ト電極2の表面に媚1絶縁膜3か形威される。なお、こ
の第1絶縁膜3の堆積広はECR−CVD法に限られず
、指向性を有する堆積法であればよく、例えばスパッタ
法等であってもよい。Therefore, an insulating film 3 is formed on the surfaces of the semiconductor substrate 1 and the gate electrode 2 except for this portion. Note that the method for depositing the first insulating film 3 is not limited to the ECR-CVD method, but may be any deposition method that has directivity, such as a sputtering method.
そして、第1絶縁膜3を例えば反応性イオンエッチング
(R I E)により、半導体基板1の表面に対して垂
直な方向から異方的に除夫ずる。これにより、第1図(
C)に示したように、第1絶縁膜3はゲート電極2の側
部に堆積した部分のみを残して除表される。Then, the first insulating film 3 is anisotropically removed in a direction perpendicular to the surface of the semiconductor substrate 1 by, for example, reactive ion etching (RIE). As a result, Figure 1 (
As shown in C), the first insulating film 3 is removed leaving only the portion deposited on the sides of the gate electrode 2.
さらに、第1図(d)に示したように、乱板表而に対し
て無指向的に第2絶縁膜5を堆積させる。Furthermore, as shown in FIG. 1(d), a second insulating film 5 is deposited non-directionally on the surface of the disordered plate.
この場合には、堆積方向に指向性のない坩積法により第
2絶縁膜5を堆積させてもよいし、堆積方向に指向性を
h゜する堆積方法で複数の方向から第2絶縁膜5を坩積
させ堆積方向の指向性を打ち消5
すようにしてもよい。そして、第1絶縁膜3を半導体基
板1の表面に対して垂直な方向から異方的に除去したの
と同様に、第2絶縁膜5を例えば反応性イオンエッチン
グ(R I E)により、半導体L(板1の表面に対し
て垂直な方向から異方的に除去する。これにより、第1
図(e)に示したように、第2絶縁膜5はゲート電極2
の側部に堆積した部分のみを残して除去される。In this case, the second insulating film 5 may be deposited by a bulk volume method with no directivity in the deposition direction, or the second insulating film 5 may be deposited from multiple directions by a deposition method with directivity in the deposition direction. It is also possible to cancel the directivity in the deposition direction by crucifying the particles. Then, in the same way that the first insulating film 3 is anisotropically removed from the direction perpendicular to the surface of the semiconductor substrate 1, the second insulating film 5 is removed by, for example, reactive ion etching (RIE) to remove the semiconductor substrate 1. L (removed anisotropically from the direction perpendicular to the surface of the plate 1. As a result, the first
As shown in Figure (e), the second insulating film 5 is connected to the gate electrode 2
is removed leaving only the part deposited on the sides.
このような工程を経ることにより、ゲート電極2の両側
部には、第1図(e)に示したように、側壁長L とL
2が互いに兄なる側壁が形戊され1
る(L >L2)。したがって、このように非対l
称の側壁を有するゲート電極2をマスクとして不純物イ
オン等を基板表面に注入してソース領域とドレイン領域
を形戊すれば、ソース領域とドレイン領域の相互間の中
央部からオフセットした位置にゲート電極が形威された
電界効果形トランジス夕を自己整合的に得ることができ
る。By going through these steps, both sides of the gate electrode 2 have sidewall lengths L and L, as shown in FIG. 1(e).
The side walls where 2 are older brothers of each other are shaped 1 (L > L2). Therefore, if the source region and the drain region are formed by implanting impurity ions into the substrate surface using the gate electrode 2 having asymmetric sidewalls as a mask, the center between the source region and the drain region can be formed. A field effect transistor having a gate electrode formed at a position offset from the surface can be obtained in a self-aligned manner.
なお、上述した失施例は、M.ESFETの製造に本発
明を適用した場合についてのものであるが、6
MOSFETの製逍に本発明を適用することもてきる。Incidentally, the above-mentioned failure example is M. Although the present invention is applied to the manufacture of an ESFET, the present invention can also be applied to the manufacture of a 6 MOSFET.
その場合には、ゲート電極2を半導体乃板]の表面に直
接形或するのではなく、半導体基板1の表面に酸化絶縁
膜等を形威し、その上にケト電極2を形成すればよい。In that case, instead of forming the gate electrode 2 directly on the surface of the semiconductor substrate, an oxide insulating film or the like may be formed on the surface of the semiconductor substrate 1, and the keto electrode 2 may be formed thereon. .
以上説明したように、本発明よればゲート電極の両側部
に形成される側壁の側壁長を互いに巣ならしめることか
でき、オフセット構遣を有する電界効果形]・ランジス
タを自己整含的に形成することができる。As explained above, according to the present invention, the sidewall lengths of the sidewalls formed on both sides of the gate electrode can be nested with each other, thereby forming a field effect transistor with an offset structure in a self-contained manner. can do.
4,図面の簡j.lliな説明
第1図は本発明による電界効果形トランジスタの製遣h
法の大施例を・』ミした工手呈区である。4. Simplification of drawings j. Fig. 1 shows the manufacturing process of a field effect transistor according to the present invention.
It is a construction district that has implemented a major example of the law.
1・・・半導体栽板、2・・・ゲート電極、3・・・第
1絶縁膜、5・・・第2絶縁膜。DESCRIPTION OF SYMBOLS 1... Semiconductor planting board, 2... Gate electrode, 3... First insulating film, 5... Second insulating film.
Claims (1)
スタを製造する方法であって、 ゲート電極が形成された基板表面に対して傾斜した方向
から指向的にゲート電極の片側側面を除いて第1絶縁膜
を堆積させる工程と、 前記ゲート電極の側部に堆積した部分を残して前記第1
絶縁膜を前記基板表面に対して垂直に異方的に除去する
工程と、 前記基板表面に対して無指向的に第2絶縁膜を堆積させ
る工程と、 前記ゲート電極の側部に堆積した部分を残して前記第2
絶縁膜を前記基板表面に対して垂直に異方的に除去する
工程とを備えた電界効果形トランジスタの製造方法。[Claims] A method for manufacturing a field effect transistor having an offset gate electrode, the method comprising: directionally extending one side of the gate electrode from a direction inclined with respect to a substrate surface on which the gate electrode is formed; depositing a first insulating film on the sides of the gate electrode, and depositing a first insulating film on the side of the gate electrode,
a step of anisotropically removing an insulating film perpendicular to the substrate surface; a step of depositing a second insulating film non-directionally with respect to the substrate surface; and a portion deposited on the side of the gate electrode. The second
A method for manufacturing a field effect transistor, comprising the step of anisotropically removing an insulating film perpendicular to the substrate surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30245289A JPH03161937A (en) | 1989-11-21 | 1989-11-21 | Manufacture of field-effect type transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30245289A JPH03161937A (en) | 1989-11-21 | 1989-11-21 | Manufacture of field-effect type transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03161937A true JPH03161937A (en) | 1991-07-11 |
Family
ID=17909108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30245289A Pending JPH03161937A (en) | 1989-11-21 | 1989-11-21 | Manufacture of field-effect type transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03161937A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000054331A1 (en) * | 1999-03-11 | 2000-09-14 | Micron Technology, Inc. | Methods of forming local interconnects and conductive lines, and resulting structure |
-
1989
- 1989-11-21 JP JP30245289A patent/JPH03161937A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000054331A1 (en) * | 1999-03-11 | 2000-09-14 | Micron Technology, Inc. | Methods of forming local interconnects and conductive lines, and resulting structure |
US6180494B1 (en) | 1999-03-11 | 2001-01-30 | Micron Technology, Inc. | Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines |
US6391726B1 (en) | 1999-03-11 | 2002-05-21 | Micron Technology, Inc. | Method of fabricating integrated circuitry |
US6610587B2 (en) | 1999-03-11 | 2003-08-26 | Micron Technology, Inc. | Method of forming a local interconnect |
US6638842B2 (en) | 1999-03-11 | 2003-10-28 | Micron Technology, Inc. | Methods of fabricating integrated circuitry |
US6797600B2 (en) | 1999-03-11 | 2004-09-28 | Micron Technology, Inc. | Method of forming a local interconnect |
US6803286B2 (en) | 1999-03-11 | 2004-10-12 | Micron Technology, Inc. | Method of forming a local interconnect |
US6982203B2 (en) | 1999-03-11 | 2006-01-03 | Micron Technology, Inc. | Method of fabricating integrated circuitry |
US7094636B2 (en) | 1999-03-11 | 2006-08-22 | Micron Technology, Inc. | Method of forming a conductive line |
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