JPH03161853A - Data processing system - Google Patents

Abstract

PURPOSE:To reduce the size and weight of a system by using a D-RAM having a write-per-bit function as a parity storage device. CONSTITUTION:The data processing system has a data storing D-RAM 103, a parity D-RAM 104, a D-RAM control circuit 105 for forming a control signal for the D-RAM and a parity control circuit 106 for controlling the write-per-bit function of the parity D-RAM and forming and checking a parity. The dynamic type sequential read/write memory (D-RAM) having the write-per-bit function is used as a storage device for storing a parity. Thereby, the writing of each bit can be attained even by a D-RAM constituted of 4 bits X 256k words. Thus, the size and weight of the system can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing system that processes data using a control program.

[Prior Art] A commonly used parity configuration is 8 data bits and 1 parity bit, so this will be taken as an example. With the recent integration of memory elements, even small systems are now equipped with large-capacity storage devices.

For example, data@32-bit processor and IM (
Consider a system using mega)byte storage.

Since 1 byte is 8 bits, the data storage device is 8M
Also, from the above ratio, the parity storage device becomes IM bit 1.

Data is accessed 32 bits at a time in 8-bit units, so the storage device configuration is 32 bit 1 x 256k
(kilo) word, parity is 4 bits x 2
It is 56k words. Therefore, 8 4-bit x 256k word type D-RAMs were used as the data storage device.
111151', it is possible to handle both 8-bit and 32-bit accesses. However, when accessing in units of 8 bits, the parity storage device is accessed in units of 1 bit. Therefore, conventionally, 1 bit x 256k word type D-R
Four AMs were used.

[Problem to be solved by the invention] As mentioned above, a 4-bit parity storage device is used.
Since the X 2 5 6 k word type could not be used, the number of elements increased, making it difficult to construct a small and lightweight system. Therefore, an object of the present invention is to provide a data processing system in which the number of elements is reduced as much as possible.

[Means for Solving the Problems] The present invention provides a data processing system comprising: a read-only storage device for storing a basic program;
A read/write storage device for storing a control program and data, a means for generating and checking parity for checking the validity of data on the storage device, and a storage device for storing the parity. , a processor that performs processing by the control program l1, and uses a dynamic sequential read/write memory (D-RAM) having a write-per-bit function as a storage device for storing the parity. The data processing system is characterized by a D-RAM having a write-per-bit function and a normal D-RAM without the write-per-bit function as a storage device for storing the parity.
It is characterized in that it can be used selectively with RAM.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. This data processing system includes an Intel 80386 microprocessor 101 as a processor, a read-only memory 102 for storing basic programs, and a D for data storage.
-RAM 103, parity D-RAM 104, generation of the D-RAM control mIB;
RAM control circuit R 1 0 5, the parity D-R
A parity control circuit 106 that controls the AM write 1...per bit function and generates and checks parity.
, a peripheral processing device 107, and a clock generator 108. An example of a D-RAM with a write-per-bit function is Toshiba's TC514268. Here, we will particularly focus on write cycles that use the write-per-bit function.

FIG. 2 is an example of a circuit diagram of the parity control circuit iM106. Further, FIG. 3 shows a timing chart 1 of the signals in FIG. 2 and the D-RAM control signal.

The procedure for using the write-per-bit function in a D-RAM having the write-per-bit function will be explained. First, when the RAS signal falls, the WE signal goes low.
If it is at the OW level, the write 1...per bit function is enabled, and which bits are allowed to be written are determined depending on the state of the data input at that time. Bits whose data level is H1gh are written, and
Bits at level w are not written to. According to the conditions determined here, data is written at the subsequent falling edge of CAS.

The microprocessor divides the 32-bit data bus into four groups of 8 bits and outputs a signal indicating which group is valid.

This is 21 of BEO#, BE1#, BE2# and BE3#
It is 3. These correspond to bits 1/0 to 7, 8 to 15, 16 to 23, and 24 to 31 of the data bus, respectively, and when this signal goes low, the corresponding data bus is enabled. Become. On the other hand, each of the four parity generation circuits 201 calculates parity for bits 0 to 7 of the data bus, 202 calculates parity for bits 8 to 15, 203 calculates parity for bits 16 to 23, and 204 calculates parity for bits 24 to 31. In this circuit, a signal MX212 for switching the address signal input to the D-RAM is obtained from the D-RAM control circuit, and thereby 205 is set to BEO# and bit 1.
・Parity from O to 7, 206 is BE1# and bit 1
・The parity of 8 to 15 is switched, 207 is switched between BE2# and bit 1, the parity of I6 to 23 is switched, and 208 is switched between BE3# and the parity of bits 24 to 31.

As a result, the data input signal of the D-RAM is output by switching between the write bit selection signal and the data to be written as shown in FIG. As a result, 4 bits x 2 5
Writing can be performed in 1-bit units even in a D-RAM with a Bk-word configuration.

In addition, if you simply use the D-RAM data input signals one bit at a time, you can create a D-RAM consisting of 1 bit x 256k words.
RAM can also be used. In this case, since the D-RAM does not have a write-per-bit function, the data at the falling edge of RAS is ignored and can be used as before without any influence.

[Effects of the Invention] By using a D-RAM having a write-per-bit function as a parity storage device, the number of elements can be reduced and the system can be made smaller and lighter.

Furthermore, if a D-RAM with a write-per-bit function is not available, it is possible to easily return to the conventional configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram example of a parity control circuit of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention.
1 is a timing chart of an embodiment of the present invention. 101...Microprocessor 102...
...Read-only memory 103...Data D
-RAM104...D-RAM1 for parity
0゛5...D-RAM control circuit 106...
... Parity control circuit 107 ... Peripheral processing unit 108 ... Clock generation line 111 ... Atre bus 112 ... Data bus 113 ... ...Control bus 201...
... Parity generation circuit 202 ... Parity generation circuit 203 ... Parity generation circuit 204
...Parity generation circuit 205...Selector 206...Selector 207...Selector 20B...Selector-9- 21 21 21 21 30 30 30 30 30 30 30 1... Processor data 2... Switching signal MX 3... Byte enable signal 4...
D-RAM data input signal 1...Processor data 1...Byte enable signal 1...
RAS signal 1...CAS signal 1...Switching signal MX 1...WE signal 1...D-RAM data manual signal and beyond
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Claims (2)

[Claims] (1) In a data processing system, a read-only storage device that stores a basic program;
A read/write storage device for storing a control program and data, a means for generating and checking parity for checking the validity of data on the storage device, and a storage device for storing the parity. , a processor that performs processing according to the control program, and a dynamic sequential read/write memory (D-RAM) having a write-per-bit function is used as a storage device for storing the parity. data processing system. (2) As a storage device for storing the parity, a D-RAM with a write-per-bit function and a normal D-RA without the write-per-bit function are used.
2. The data processing system according to claim 1, wherein M can be selectively used.