JPH0316057B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention automatically generates a synchronization signal necessary for decoding data from the transmitting side on the receiving side by sending a signal at a predetermined bit rate from the transmitting side. The present invention relates to a synchronization signal creation method that can be created in the following manner.

2. Description of the Related Art When transmitting and receiving data between a transmitting side and a receiving side, the receiving side requires a synchronization signal corresponding to the bit rate of the signal from the transmitting side. Conventionally, the receiving side is provided with, for example, a reference oscillator such as a crystal oscillator, a programmable divider for dividing the frequency of its output signal, and a setting means for manually setting the frequency division ratio of the programmable divider.
The output signal of the programmable divider is used as a synchronization signal. In other words, conventionally, a synchronization signal with a frequency corresponding to the bit rate of the transmitting side is created by manually operating the setting means, so this is not applicable to systems where the bit rate needs to be changed frequently, or when the transmitting side and the receiving side In systems where the two sides are separated, there is a problem that operation becomes cumbersome.

Problems to be Solved by the Invention The present invention solves the above-mentioned problems, and its purpose is to enable the receiving side to automatically create a synchronization signal necessary for decoding data from the transmitting side. The purpose is to do so.

Means for Solving the Problems In order to solve the above-mentioned drawbacks, the present invention provides a system for transmitting data from a transmitting side to a receiving side at a first or second bit rate. Detection in which a bit rate setting signal having a frequency of 1/2 of the bit rate frequency of the data to be sent is sent before the start of transmission, and the receiving side outputs a signal at the rising and falling edges of the bit rate setting signal from the transmitting side. means, a phase comparator that outputs a voltage corresponding to the phase difference between the signal from the detection means and the output signal of the programmable divider, a low-pass filter when the output of the phase comparator is input, and an output voltage of the low-pass filter. a voltage-controlled oscillator that applies a signal with a frequency corresponding to the frequency to the programmable divider; and a voltage control oscillator that applies a signal with a frequency corresponding to The division ratio of 1/n or 1/n×
control means for selectively controlling f1/f2, where n is a natural number, f1<f2, and f1 and f2 are first and second bit rate frequencies, respectively;
The output signal of the programmable divider is used as a synchronization signal for the received data on the receiving side.

Function A phase locked loop (PLL) is formed by a phase comparator, a low-pass filter, a voltage controlled oscillator, and a programmable divider. ) is configured. Further, the frequency division ratio of the programmable divider is controlled by the control means so that the output signal of the programmable divider becomes the bit rate frequency of the data sent from the transmitting side. Therefore, by sending a bit rate setting signal having a frequency that is half the bit rate frequency of the data to be transmitted from the transmitting side before starting data transmission, the PLL is locked and the programmable divider is locked even when data transmission starts. Since the output signal of the programmable divider does not change, the output signal of the programmable divider can be used as a synchronization signal on the receiving side.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention.
This is for the case where data can be sent at two types of bit rates of 4800 bit/sec. In the same figure, 3 is a processing unit composed of a microprocessor, etc., 4 is a detection circuit composed of an exclusive OR gate EX-OR, a resistor R, and a capacitor C;
5 is a phase comparator, 6 is a low-pass filter, 7 is a voltage controlled oscillator, 8 is a programmable divider,
COM1 and COM2 are comparators, IN is an inverter,
NAND1 and NAND2 are NAND gates.
Note that the comparators COM1 and COM2 set their output signals f and g to "1" while the level of the signal applied to the + terminal is higher than the level of the signal applied to the - terminal.
That is. Further, the programmable divider 8 sets the frequency division ratio N to 1 when the output signal h of the flip-flop consisting of NAND gates NAND1 and NAND2 is "1", and sets the frequency division ratio N to 1/2 when the signal h is "0". There is something that does. Further, the phase comparator 5, low pass filter 6, voltage controlled oscillator 7 and programmable divider 8 constitute a phase locked loop (PLL).

2 is a voltage-frequency characteristic diagram of the voltage controlled oscillator 7, where f1 and f2 are the lowest and highest oscillation frequencies of the voltage controlled oscillator 7, respectively. Also, f0 is
The frequency is approximately in the center of f1 and f2, for example, it is set to 9600Hz, and f1 and f2 are 4800<
It is set to satisfy the relationship f1<9600<f2<19200. In addition, the threshold value Va of the comparator COM1 is set between the voltages V0 and V1 which make the frequencies of the voltage controlled oscillator 7 ff0 and f1, and the comparator
The threshold value Vb of COM2 is the frequency of the voltage comparator 7.
It is set between voltages V0 and V2 which are set to 0 and f2. That is, comparators COM1, COM
2 thresholds Va and Vb are V1<Va<V0, V0<Vb
<V2 is set to satisfy the relationship.

When sending side 1 sends data to receiving side 2,
Prior to transmitting data, a signal with a frequency corresponding to the bit rate of the data to be transmitted (hereinafter referred to as a bit rate setting signal) is transmitted to the receiving side via a transmission path. This bit rate setting signal is applied to the processing section 3 and the detection circuit 4, and the detection circuit 4 outputs a signal having a pulse width determined by the values of the resistor R and the capacitor C at the rising and falling edges.

For example, when transmitting data to the receiving side 2 at a bit rate of 9600 bits/sec, the transmitting side 1 transmits a bit rate setting signal consisting of repeating "1" and "0" at 4800 Hz before transmitting the data. this
When the bit rate setting signal of 4800 Hz is supplied, the detection circuit 4 sets its output signal a to "1" at the rise and fall of the signal and applies it to the phase comparator 5. The transmission comparator 5 outputs a signal b corresponding to the phase difference between the output signal a of the detection circuit 4 and the output signal b of the programmable divider 8,
applies to the voltage controlled oscillator 7 the signal c from which the high frequency component superimposed on the signal b has been removed.

Below, the output voltage Vx of the low-pass filter just before the 4800Hz bit rate setting signal is applied is (1)
If Va＜Vx＜Vb, (2) If Vx≦Va, (3) Vx
The operation of the receiving side 2 when ≧Vb will be explained.

(1) When Va<Vx<Vb Immediately after the bit rate setting signal is applied, the output signals f and g of comparators COM1 and COM2 are
are both “1”, and the NAND gate NAND1,
The output signal h of the flip-flop consisting of NAND2 becomes "0" or "1".

At this time, the flip-flop output signal h is “0”
If so, the frequency division ratio of the programmable divider 8 will be 1/2 as described above, and the frequency of its output signal e will be about 4800 Hz. However, at this time, the frequency of the output signal a of the detection circuit 4 is 9600Hz.
Therefore, the output voltage Vx of the low-pass filter 6
gradually increases to exceed the threshold value Vb of the comparator COM2, and the output signals f and g of the comparators COM1 and COM2 become "1" and "0", respectively. As a result, the output signal h of the flip-flop consisting of NAND gates NAND1 and NAND2 becomes "1", and the frequency division ratio of the programmable divider 8 becomes 1/1.
becomes. As a result, the output voltage Vx of the low-pass filter 6 gradually decreases to V0, and the output signal d of the voltage controlled oscillator 7 and the programmable divider 8
The frequency of the output signal e is 9600Hz. Also, since the output voltage Vx of the low-pass filter 6 becomes V0, the output signals f and g of the comparators COM1 and COM2
are both “1”, and the programmable divider 8
The frequency division ratio is maintained at 1/1.

Further, if the output signal h of the flip-flop consisting of NAND gates NAND1 and NAND2 becomes "1" immediately after the bit rate setting signal is applied, the frequency division ratio of the programmable divider 8 becomes 1/1, and the output signal e The frequency gradually approaches 9600Hz and is locked at 9600Hz.

(2) When Vx≦Va Immediately after the bit rate setting signal is applied, the output signals f and g of the comparators COM1 and COM2 become “0” and “1”, and the NAND gate NAND
The output signal h of the flip-flop consisting of NAND1 and NAND2 becomes "0". As a result, the frequency division ratio of the programmable divider 8 is 1/2 as described above.
Therefore, the frequency of the output signal e is smaller than 4800Hz. However, at this time, since the frequency of the output signal a of the detection circuit 4 is 9600Hz, the output voltage Vx of the low-pass filter 6 gradually increases and exceeds the threshold value Va of the comparator COM1, and the comparators COM1 and COM2 The output signals f and g of the flip-flop become "1" and "1", respectively, the output signal h of the flip-flop is held at "0", and the frequency division ratio of the programmable divider 8 is held at 1/2. Therefore, since the frequency of the output signal e of the programmable divider 8 is 9600Hz or less in this case as well,
The output voltage Vx of the low-pass filter 6 further increases and exceeds the threshold value Vb of the comparator COM2.
As a result, the output signals f and g of the comparators COM1 and COM2 become "1" and "0", respectively, the output signal h of the flip-flop becomes "1", the frequency division ratio of the programmable divider 8 becomes 1/1, and the programmable The frequency of the output signal e of the divider 8 is
9600Hz or higher. As a result, the output voltage Vx of the low-pass filter 6 gradually decreases to the comparator COM2.
The frequency division ratio of the programmable divider 8 is maintained at 1/1, and the output signal e
The frequency gradually approaches 9600Hz and is locked at 9600Hz.

(3) When Vx≧Vb Immediately after the bit rate setting signal is applied, the output signals f and g of comparators COM1 and COM2 become “1” and “0”, respectively, and the output signal h of the flip-flop becomes “1”. ” becomes. As a result, the frequency division ratio of the programmable divider 8 becomes 1/1,
The frequency of the output signal e is 9600Hz or more. However, at this time, since the frequency of the output signal a of the detection circuit 4 is 9600Hz, the output voltage Vx of the low-pass filter 6 gradually decreases to V0, and the output signal d of the voltage controlled oscillator 7 and the output of the programmable divider 8 The frequency of signal e is 9600Hz. Also,
Since the output voltage Vx of the low-pass filter 6 becomes V0, the output signals f and g of the comparators COM1 and COM2 both become "1", and the frequency division ratio of the programmable divider 8 is maintained at 1/1.

As mentioned above, when a 4800 Hz bit rate setting signal is applied from the transmitting side, the frequency division ratio of the programmable divider 8 becomes 1/1, and the output signal d of the voltage controlled oscillator 7 and the output signal e of the programmable divider 8 will be locked to 9600Hz.

Further, when transmitting data to the receiving side 2 at a bit rate of 4800 bit/sec, the transmitting side transmits a bit rate setting signal consisting of repeating "1" and "0" at a frequency of 2400 Hz prior to transmitting the data. As described above, the detection circuit 4 sets its output signal a to "1" at the rising and falling edges of the bit rate setting signal.
do.

Below, the output voltage Vx of the low-pass filter just before the 2400Hz bit rate setting signal is applied is (1)
If Va＜Vx＜Vb, (2) If Vx≦Va, (3) Vx
The operation of the receiving side 2 when ≧Vb will be explained.

(1) When Va<Vx<Vb Immediately after the bit rate setting signal is applied, the output signals f and g of comparators COM1 and COM2 are
are both “1”, and the NAND gate NAND1,
The output signal h of the flip-flop consisting of NAND2 becomes "0" or "1".

At this time, the flip-flop output signal h is “0”
If so, the frequency division ratio of the programmable divider 8 will be 1/2 as described above, and the frequency of its output signal e will be about 4800 Hz. However, at this time, the frequency of the output signal a of the detection circuit 4 is 4800Hz.
Therefore, the output voltage Vx of the low-pass filter 6
gradually approaches V0, and the frequency of the output signal d of the voltage controlled oscillator gradually approaches 9600Hz,
Hz locked and programmable divider 8
The frequency of the output signal e gradually approaches 4800Hz,
Locked at 4800Hz.

Immediately after the bit rate setting signal is applied, the output signal h of the flip-flop becomes "1".
, the frequency division ratio of the programmable divider 8 will be 1/1, and the frequency of its output signal e will be approximately 9600 Hz. However, at this time, since the frequency of the output signal a of the detection circuit 4 is 4800Hz, the output voltage Vx of the low-pass filter 6 gradually decreases to below the threshold value Va of the comparator COM1, and the comparator
The output signals f and g of COM1 and COM2 become "0" and "1", respectively. As a result, the output signal h of the flip-flop becomes "0", and the frequency division ratio of the programmable divider 8 becomes 1/2. As a result, the output voltage Vx of the low-pass filter 6 gradually increases and approaches V0, and the frequency of the output signal d of the voltage controlled oscillator 7 gradually approaches 9600Hz.
It is locked at 9600Hz, and the frequency of the output signal e of the programmable divider 8 gradually approaches 4800Hz and is locked at 4800Hz.

(2) When Vx≦Va Immediately after the bit rate setting signal is applied, the output signals f and g of the comparators COM1 and COM2 become “0” and “1”, and the NAND gate NAND
The output signal h of the flip-flop consisting of NAND1 and NAND2 becomes "0". As a result, the frequency division ratio of the programmable divider 8 is 1/2 as described above.
Therefore, the frequency of the output signal e is 4800Hz or less. At this time, since the frequency of the output signal a of the detection circuit 4 is 4800Hz, the output voltage Vx of the low-pass filter 6 gradually approaches V0, and the frequency of the output signal d of the voltage controlled oscillator gradually approaches 9600Hz, and locks at 9600Hz. Also, the frequency of the output signal e of the programmable divider 8 gradually approaches 4800 Hz and is locked at 4800 Hz.

(3) When Vx≧Vb Immediately after the bit rate setting signal is applied, the output signals f and g of comparators COM1 and COM2 become “1” and “0”, respectively, and the output signal h of the flip-flop becomes “1”. ” becomes. As a result, the frequency division ratio of the programmable divider 8 becomes 1/1,
The frequency of the output signal e is 9600Hz or more. However, at this time, since the frequency of the output signal a of the detection circuit 4 is 4800Hz, the output voltage Vx of the low-pass filter 6 gradually decreases to the threshold of the comparator COM2.
Vb or less. As a result, comparator COM1,
The output signals f and g of COM2 both become “1”,
The frequency division ratio of the programmable divider 8 is maintained at 1/1, and the frequency of its output signal e is also approximately 9600 Hz. Therefore, the output voltage of the low-pass filter 6
Vx further decreases to below the threshold value Va of comparator COM1, and the output signals f of comparators COM1 and COM2,
g becomes "0" and "1", respectively, the frequency division ratio of the programmable divider 8 becomes 1/2, and the frequency of the output signal e becomes 4800 Hz or less. As a result,
The output voltage Vx of the low-pass filter 6 gradually increases and exceeds the threshold value Va of the comparator COM1, and the comparator
Output signals f and g of COM1 and COM2 are both “1”
Therefore, the division ratio of the programmable divider is 1/
2, the frequency of the output signal d of the voltage controlled oscillator 7 is locked at 9600 Hz, and the frequency of the output signal e of the programmable divider 8 becomes 4800 Hz.

As mentioned above, when a bit rate setting signal of 2400 Hz is applied from the transmitting side, the frequency division ratio of the programmable divider 8 becomes 1/2, and the frequency of the output signal d of the voltage controlled oscillator 7 is locked to 9600 Hz. The frequency of the output signal e of the programmable divider 8 is 4800Hz.

In this way, the frequency of the output signal e of the programmable divider 8 corresponds to the bit rate of the data from the transmitter 1, so by using this signal e as a synchronization signal, the transmitter It becomes possible to decipher the data from 1.

Effects of the Invention As explained above, the present invention provides a system for transmitting data from a transmitting side to a receiving side at a first or second bit rate (9600 bit/sec or 4800 bit/sec in the embodiment). Before starting data transmission, the transmitting side sends out a bit rate setting signal having a frequency that is half the bit rate frequency of the data to be sent, and the receiving side adjusts the bit rate setting signal at the rising and falling edges of the bit rate setting signal from the transmitting side. a phase comparator that outputs a voltage corresponding to a phase difference between the signal from the detection means and the output signal of the programmable divider;
a low-pass filter that receives the output of the phase comparator as an input; a voltage-controlled oscillator that applies a signal with a frequency corresponding to the output voltage of the low-pass filter to the programmable divider; The frequency division ratio of the programmable divider is set to 1/n or 1/n×f1/f2 so that the frequency of the output signal becomes the bit rate frequency of the data to be sent out.
control means for selectively controlling n.
is a natural number, f1<f2, f1 and f2 are the first and second bit rate frequencies, respectively, and the output signal of the programmable divider is used as a synchronization signal for the received data on the receiving side. Since it is possible to automatically create a synchronization signal based on data from the transmitting side, it has the advantage of improved operability compared to the conventional example. Further, according to the present invention, the frequency division ratio of the programmable divider is set to 1/n according to the first or second bit rate.
Since the oscillation frequency of the voltage controlled oscillator is always stabilized around n x f2, there is no need to use a voltage controlled oscillator with a wide operating range. This is advantageous in terms of cost, and can also shorten the time it takes for the PLL to lock.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
The figure is a voltage-frequency characteristic diagram of the voltage controlled oscillator 7. 1 is a transmitting side, 2 is a receiving side, 3 is a processing section, 4 is a detection circuit composed of an exclusive OR gate EX-OR, a resistor R, and a capacitor C, 5 is a phase comparator, 6 is a low-pass filter, 7 is a voltage controlled oscillator, 8 is a programmable divider, COM1,
COM2 is a comparator, IN is an inverter, NAND1,
NAND2 is a NAND gate.

Claims (1)

[Claims] 1. In a system in which data is transmitted from a transmitting side to a receiving side at a first or second bit rate, the transmitting side transmits data at 1/2 of the bit rate frequency of the data to be transmitted before starting data transmission. A bit rate setting signal having a frequency of a phase comparator that outputs a voltage corresponding to the phase difference with the signal; a low-pass filter that receives the output of the phase comparator; and a voltage that applies a signal with a frequency corresponding to the output voltage of the low-pass filter to the programmable divider. Based on the control oscillator and the output signal of the low-pass filter, the frequency division ratio of the programmable divider is set to 1/n or 1/n× so that the frequency of the output signal of the programmable divider becomes the bit rate frequency of the data to be sent out. control means for selectively controlling f1/f2, where n is a natural number;
A synchronization signal generation method characterized in that f1<f2, f1 and f2 are first and second bit rate frequencies, respectively, and the output signal of the programmable divider is used as a synchronization signal for received data on the receiving side. .