JPH031560A - Resin sealed circuit board - Google Patents
Resin sealed circuit boardInfo
- Publication number
- JPH031560A JPH031560A JP1243518A JP24351889A JPH031560A JP H031560 A JPH031560 A JP H031560A JP 1243518 A JP1243518 A JP 1243518A JP 24351889 A JP24351889 A JP 24351889A JP H031560 A JPH031560 A JP H031560A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- circuit board
- transfer molding
- sealed
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 47
- 239000011347 resin Substances 0.000 title claims abstract description 47
- 238000007789 sealing Methods 0.000 claims abstract description 32
- 230000001681 protective effect Effects 0.000 claims abstract description 26
- 238000001721 transfer moulding Methods 0.000 claims description 33
- 238000005259 measurement Methods 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 27
- 239000000463 material Substances 0.000 abstract description 8
- 238000012546 transfer Methods 0.000 abstract description 6
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＩＣカード等に使用される薄型パ・ンケージ
構造の樹脂封止用回路基板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a resin-sealed circuit board with a thin package structure used for IC cards and the like.
（従来の技術）
従来、ＩＣカードに使用される薄型パッケージの厚さは
０．５〜１−程度であるが、近年では、更に薄型で精度
の高いパッケージ構造が要求されている。(Prior Art) Conventionally, the thickness of a thin package used for an IC card is about 0.5 to 1-1, but in recent years there has been a demand for an even thinner and more precise package structure.
以下、このような従来の樹脂封止用回路基板の製造方法
について、第４図を用いて説明する。Hereinafter, a method of manufacturing such a conventional resin-sealed circuit board will be explained using FIG. 4.
まず、第４図（ａ）に示すように、印刷配線板１に凹部
２を設け、上面及び下面に配線３を施し、スルーホール
４を介してそれらの配線を接続する。First, as shown in FIG. 4(a), a recess 2 is provided in a printed wiring board 1, wiring 3 is provided on the upper and lower surfaces, and these wirings are connected via through holes 4.
次に、第４図（ｂ）に示すように、接着剤５を用いて凹
部２上に半導体チップ６を固着し、ワイヤ７によってそ
の半導体チップ６と印刷配線板１の上面の配線３とを接
続する。Next, as shown in FIG. 4(b), a semiconductor chip 6 is fixed onto the recess 2 using an adhesive 5, and a wire 7 connects the semiconductor chip 6 to the wiring 3 on the top surface of the printed wiring board 1. Connecting.
次に、このようにして形成された樹脂封止用回路基板を
、第４図（ｃ）に示すように、下金型８と上金型９間に
セントする。Next, the resin-sealed circuit board thus formed is placed between the lower mold 8 and the upper mold 9, as shown in FIG. 4(c).
次に、第４図（ｄ）に示すように、封止樹脂１０を用い
たトランスファ成形により、半導体チップ６を樹脂封止
する。Next, as shown in FIG. 4(d), the semiconductor chip 6 is resin-sealed by transfer molding using the sealing resin 10.
また、第８図に示すような樹脂封止用回路基板の製造方
法も公知である。この種のものは、例えば特開昭５８−
１５９号に記載されている。Furthermore, a method of manufacturing a resin-sealed circuit board as shown in FIG. 8 is also known. This kind of thing is, for example, JP-A-58-
It is described in No. 159.
まず、第８図（ａ）に示すように、印刷配線板１１に凹
部を設け、上面及び下面に配線１２を施し、スルーホー
ル１３を介してそれらの配線間を接続する。First, as shown in FIG. 8(a), a recessed portion is provided in a printed wiring board 11, wirings 12 are provided on the upper and lower surfaces, and the wirings are connected via through holes 13.
次に、第８図（ｂ）に示すように、接着剤１４を用いて
凹部上に半導体チップ１５を固着し、ワイヤ１６によっ
てその半導体チップ１５と印刷配線板１１の上面の配線
１２とを接続する。Next, as shown in FIG. 8(b), the semiconductor chip 15 is fixed onto the recess using an adhesive 14, and the semiconductor chip 15 is connected to the wiring 12 on the top surface of the printed wiring board 11 using a wire 16. do.
次に、第８図（ｃ）に示すように、印刷配線板１１の上
面に樹脂枠１７を設ける。Next, as shown in FIG. 8(c), a resin frame 17 is provided on the upper surface of the printed wiring board 11.
次に、このようにして形成された樹脂封止用回路基板を
、第８図（ｄ）に示すように、下金型１８と上金型１９
間にセットする。Next, as shown in FIG. 8(d), the circuit board for resin sealing formed in this way is placed into the lower mold 18 and the upper mold 19.
set in between.
次に、第８図（ｅ）に示すように、封止樹脂２０を用い
たトランスファ成形により、半導体チップ１５を樹脂封
止する。Next, as shown in FIG. 8(e), the semiconductor chip 15 is resin-sealed by transfer molding using the sealing resin 20.
第１２図は従来の樹脂封止用回路基板に半導体素子を搭
載したＣＯＢ （チップ・オン・ボード）の電気的測定
状態断面図である。FIG. 12 is a sectional view of a COB (chip on board) in which a semiconductor element is mounted on a conventional resin-sealed circuit board in an electrically measured state.
この図において、７６はＣＯＢ、７７は金属パターンの
外部接続用リード端子、７８は測定用ポゴピン、７９は
測定用ポゴピン７８を固定する絶縁材である。In this figure, 76 is a COB, 77 is a metal pattern lead terminal for external connection, 78 is a measurement pogo pin, and 79 is an insulating material for fixing the measurement pogo pin 78.
この図に示すように、従来では外部接続用リード端子７
７に測定用ポゴピン７８を接触させて電気的測定を行っ
ていた。As shown in this figure, conventionally, external connection lead terminal 7
7 was brought into contact with a measuring pogo pin 78 to perform electrical measurements.
（発明が解決しようとする課題）
しかしながら、第４図に示す方法によれば、第４図の（
ｃ）工程において、配線３が上金型９と下金型８とで挟
持されることにより、第５図（ｉ）から第５図（１１）
に示すように圧迫され、第６図に示すような配線の段切
れ３ａを起こしたり、第７図に示すように、配線３面に
金型の圧痕３ｂが残るといった問題があった。(Problem to be solved by the invention) However, according to the method shown in FIG.
c) In the process, the wiring 3 is sandwiched between the upper mold 9 and the lower mold 8, so that the wiring 3 is sandwiched between the upper mold 9 and the lower mold 8, so that
As shown in FIG. 7, there were problems in that the pressure was applied, causing breakage of the wiring 3a as shown in FIG. 6, and leaving impressions 3b of the mold on the surface of the wiring 3 as shown in FIG.
また、第８図に示す方法の場合には、樹脂枠１７がクヨ
ション材として作用するものの、上金型１９と下金型１
８による圧力が樹脂枠１７に集中的に作用するため、第
９図に示すように、前記した第６図の場合と同じような
配線１２の断切れが起こったり、金型の圧痕が残るとい
った問題があった。In addition, in the case of the method shown in FIG. 8, although the resin frame 17 acts as a cushion material, the upper mold 19 and the lower mold 1
8 acts intensively on the resin frame 17, as shown in FIG. 9, the wiring 12 may be cut off as in the case of FIG. 6, or mold impressions may remain. There was a problem.
更に、従来の半導体構造では、第１２図に示すように、
外部接続用リード端子７７に測定用ポゴピン７８を接触
させて電気的測定を行っているため、外部接続用リード
端子７７に傷が付き易いといった問題があった。Furthermore, in the conventional semiconductor structure, as shown in FIG.
Since the measurement pogo pin 78 is brought into contact with the external connection lead terminal 77 for electrical measurement, there is a problem in that the external connection lead terminal 77 is easily damaged.
本発明は、以上述べた問題点を除去し、配線の１員傷を
なくすと共に、薄型化を図り得る樹脂封止用回路基板を
提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a resin-sealed circuit board that eliminates the above-mentioned problems, eliminates single-layer damage to wiring, and can be made thinner.
（課題を解決するための手段）
本発明は、上記目的を達成するために、略平行に配列さ
れた２本の外枠と、該外枠間に位置し、サポートバーで
支持される回路配線基板を連設し、上面には保護膜がパ
ターニングされ、トランスファ成形により封止される樹
脂封止用回路基板において、前記回路配線基板のトラン
スファ成形用金型のキャビティ周辺部、トランスファ成
形用ゲート及びランナー部並びに前記外枠に前記保護膜
をパターニングするようにしたものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides two outer frames arranged substantially in parallel, and circuit wiring located between the outer frames and supported by a support bar. In a circuit board for resin sealing in which substrates are arranged in series, a protective film is patterned on the upper surface, and the circuit board is sealed by transfer molding, the circuit wiring board has a peripheral part of the cavity of a mold for transfer molding, a gate for transfer molding, and The protective film is patterned on the runner portion and the outer frame.
また、本発明は、略平行に配列された２本の外枠と、該
外枠間に位置し、サポートバーで支持される回路配線基
板を連設し、トランスファ成形により封止される樹脂封
止用回路基板において、前記回路配線基板に形成される
導体パターンと、前記外枠に形成される測定用端子とを
有し、トランスファ成形用金型が前記導体パターン及び
測定用端子に当接するようにしたものである。Further, the present invention provides a resin sealing method in which two outer frames arranged substantially parallel to each other, a circuit wiring board positioned between the outer frames and supported by a support bar, are connected, and the resin sealing board is sealed by transfer molding. The stop circuit board has a conductor pattern formed on the circuit wiring board and a measurement terminal formed on the outer frame, and the transfer molding die is in contact with the conductor pattern and the measurement terminal. This is what I did.
（作用）
本発明によれば、上記のように、配線基板の適切な箇所
に保護膜を形成し、トランスファ成形を行うようにした
ので、金型による配線の損傷をなくすと共に、基板をカ
ード化した場合の剥離をなくし、薄型の樹脂封止用回路
基板を得ることができる。(Function) According to the present invention, as described above, a protective film is formed at appropriate locations on the wiring board and transfer molding is performed, thereby eliminating damage to the wiring caused by the mold and converting the board into a card. It is possible to eliminate the peeling that would otherwise occur and obtain a thin resin-sealed circuit board.
また、ガラスエポキシ等からなる半導体素子搭載基板の
外部接続用端子以外の外枠部分に測定用端子を設け、ト
ランスファ成形用金型により配線に局部的な圧力が加わ
るのを防ぎ、トランスファ成形時の配線の損傷をなくす
ことができる。In addition, measurement terminals are provided on the outer frame part of the semiconductor element mounting board made of glass epoxy etc. other than the external connection terminals, to prevent local pressure from being applied to the wiring by the transfer molding mold, and to prevent the transfer molding from applying local pressure to the wiring. Damage to wiring can be eliminated.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の第１実施例を示す樹脂封止用回路基板
の全体平面図、第２図は本発明の第１実施例を示す樹脂
封止用回路基板の構成図であり、第２図（Ａ）はその平
面図、第２図（Ｂ）はその断面図である。FIG. 1 is an overall plan view of a circuit board for resin sealing according to a first embodiment of the present invention, and FIG. 2 is a configuration diagram of a circuit board for resin sealing according to a first embodiment of the present invention. FIG. 2(A) is a plan view thereof, and FIG. 2(B) is a sectional view thereof.
これらの図において、多連の配線基板部２１に凹部２２
を形成し、その凹部２２に半導体素子２５を搭載する。In these figures, there are recesses 22 in the multiple wiring board parts 21.
is formed, and a semiconductor element 25 is mounted in the recess 22.
また、従来のように、配線基板部２１の表側には配線パ
ターン２３、裏側にはリード端子２４を形成する。そし
て、ワイヤ２６により半導体素子２５と配線基板部２１
を接続し、封止樹脂２７を用いて樹脂封止する。Further, as in the conventional case, a wiring pattern 23 is formed on the front side of the wiring board section 21, and a lead terminal 24 is formed on the back side. Then, the wire 26 connects the semiconductor element 25 to the wiring board section 21.
are connected and resin-sealed using a sealing resin 27.
更に、本発明においては、トランスファ成形用金型のキ
ャビティ周辺部３１、トランスファ成形用ゲート及びラ
ンナー部３０、外枠３３にそれぞれ保護膜、例えば厚さ
２０μｍのエポキシ系樹脂からなるソルダーレジストを
塗布する。ここで、トランスファ成形用ゲート及びラン
ナー部３０の保護膜の幅は、ゲート幅より広く形成する
。これは、樹脂封止後のゲート部の剥離を容易にすると
ともに、ゲ−１１１による基材メクレ傷の発生等を防止
するためである。Furthermore, in the present invention, a protective film, for example, a solder resist made of epoxy resin with a thickness of 20 μm, is applied to the peripheral portion 31 of the cavity of the transfer mold, the gate and runner portion 30 for transfer molding, and the outer frame 33, respectively. . Here, the width of the protective film of the transfer molding gate and runner section 30 is formed wider than the gate width. This is to facilitate peeling off of the gate portion after resin sealing and to prevent scratches on the base material caused by the gate 111.
また、保護膜を施すことにより金型の圧力が分散される
ので、配線パターン２３の断切れを防止し、配線パター
ン２３と基材の段差を少なくすると共に、保護膜がクツ
ション材になるため、封止樹脂２７の流れ出しを防止す
ることができる。In addition, by applying the protective film, the pressure of the mold is dispersed, which prevents the wiring pattern 23 from breaking and reduces the level difference between the wiring pattern 23 and the base material. It is possible to prevent the sealing resin 27 from flowing out.
更に、トランスファ成形用金型のキャビティ周辺部３１
において保護膜として用いる樹脂の注入口と略反対側の
一部に切り離し部３２を設ける。このように構成するこ
とにより、樹脂封止時において、保護膜と基材の段差が
封止時における金型のエアーベントとして機能する。Furthermore, the cavity peripheral portion 31 of the transfer molding mold
A cutoff portion 32 is provided at a portion on the side substantially opposite to the injection port for the resin used as the protective film. With this configuration, during resin sealing, the step between the protective film and the base material functions as an air vent for the mold during sealing.
次に、本発明の第１実施例の樹脂封止用回路基板の製造
方法を第３図を用いて説明する。Next, a method for manufacturing a resin-sealed circuit board according to a first embodiment of the present invention will be described with reference to FIG.
まず、第３図（ａ）に示すように、凹部４２を有する配
線基板部４１、サポートバー４５及び外枠４６を有する
基板を用意する。First, as shown in FIG. 3(a), a board having a wiring board section 41 having a recess 42, a support bar 45, and an outer frame 46 is prepared.
次に、第３図（ｂ）に示すように、その基板のトランス
ファ成形用金型のキャビティ周辺部４９、トランスノア
成形用ゲート及びランナー部４８並びに前記外枠４６に
、保護膜としての樹脂４７を塗布してパターニングする
。この時、トランスファ成形用金型のキャビティ周辺部
４９において、保護膜として用いる樹脂の注入口と略反
対側に切り離し部５０を形成する。なお、第３図（ｂ）
′は第３図（ｂ）のＡ−Ａ線断面図である。また、ここ
で、４３は配線パターン、４４はスルホールである。Next, as shown in FIG. 3(b), a resin 47 as a protective film is applied to the peripheral part 49 of the cavity of the transfer molding die of the substrate, the gate and runner part 48 for transnor molding, and the outer frame 46. Apply and pattern. At this time, in the cavity periphery 49 of the transfer molding die, a cutoff portion 50 is formed on the side substantially opposite to the injection port for the resin used as the protective film. In addition, Fig. 3(b)
' is a sectional view taken along the line A--A in FIG. 3(b). Further, here, 43 is a wiring pattern, and 44 is a through hole.
次に、第３図（ｃ）に示すように、接着剤５１を用いて
配線基板部４１の凹部４２に半導体素子５２を固着し、
ワイヤ５３によって半導体素子５２と配線基板部４１と
を接続する。Next, as shown in FIG. 3(c), the semiconductor element 52 is fixed in the recess 42 of the wiring board part 41 using an adhesive 51,
A wire 53 connects the semiconductor element 52 and the wiring board section 41 .
次に、このようにして形成された樹脂封止用回路基板を
、第３図（ｄ）に示すように、上金型５５と下金型５４
とで挟持し、樹脂封止する。Next, as shown in FIG. 3(d), the circuit board for resin sealing formed in this way is placed between an upper mold 55 and a lower mold 54.
and sandwich it and seal it with resin.
次に、第３図（ｅ）に示すように、封止樹脂５６を用い
たトランスファ成形によって半導体素子５２を樹脂封止
した後、トランスファ成形用ゲート及びランナー部４８
と外枠４６を除去する。この時、例えばトランスファ成
形用ゲート及びランナー部４８の封止樹脂５６′は、押
さえ板（図示なし）で挟持した後に折り曲げることによ
り、容易に、しかも確実に剥離することができる。Next, as shown in FIG. 3(e), after the semiconductor element 52 is resin-sealed by transfer molding using a sealing resin 56, the transfer molding gate and runner portion 48 are sealed.
and remove the outer frame 46. At this time, for example, the sealing resin 56' of the transfer molding gate and runner section 48 can be easily and reliably peeled off by holding it between pressing plates (not shown) and then bending it.
第１０図は本発明の第２実施例を示す樹脂封止用回路基
板の構成図であり、第１０図（Ａ）はその平面図、第１
Ｏ図（Ｂ）はその断面図である。FIG. 10 is a configuration diagram of a resin-sealed circuit board showing a second embodiment of the present invention, and FIG. 10(A) is a plan view thereof, and FIG.
Figure O (B) is its cross-sectional view.
この実施例は、前記した実施例のように配線基板部４１
へ凹部４２を設けるのではなく、平坦な配線基板部６０
上に半導体素子６３を載置し、ワイヤ６４により配線基
板部６０上の配線パターン６１と半導体素子６３とを接
続するものである。また、第１０図（Ａ）に示すように
、トランスファ成形用ゲート及びランナー部７１、トラ
ンスファ成形用金型のキャビティ周辺部７２、及び外枠
（図示なし）にはそれぞれ保護膜としての樹脂を塗布す
る。ここで、６２は配線パターン、７２′ は切り離し
部である。In this embodiment, the wiring board section 41 is similar to the embodiment described above.
Rather than providing a recessed portion 42, a flat wiring board portion 60 is provided.
A semiconductor element 63 is placed thereon, and the wiring pattern 61 on the wiring board section 60 and the semiconductor element 63 are connected by wires 64. In addition, as shown in FIG. 10(A), a resin as a protective film is applied to the transfer molding gate and runner part 71, the cavity peripheral part 72 of the transfer mold, and the outer frame (not shown). do. Here, 62 is a wiring pattern, and 72' is a cutout portion.
第１１図は本発明の第３実施例を示す樹脂封止用回路基
板に半導体素子を搭載し、モールド金型で挟んだ時の断
面図である。FIG. 11 is a sectional view showing a third embodiment of the present invention when a semiconductor element is mounted on a resin-sealed circuit board and sandwiched between molds.
この実施例では、図に示すように、基板の裏面の配線パ
ターン４３以外の箇所にも保護膜としての樹脂８７を塗
布する。なお、その他の構成要素については、第３図（
ｄ）に示したものと同様である。In this embodiment, as shown in the figure, a resin 87 as a protective film is applied to areas other than the wiring pattern 43 on the back surface of the substrate. The other components are shown in Figure 3 (
This is similar to that shown in d).
このように構成することにより、前記実施例においては
、樹脂封止用回路基板の上面のみしか保護膜としての樹
脂を塗布しないため、その樹脂の伸縮による回路基板の
反り（曲がり）が生じる恐れがあるが、本実施例ではこ
れを除去することができる。With this configuration, in the above embodiment, the resin as a protective film is applied only to the upper surface of the resin-sealed circuit board, so there is a risk that the circuit board may warp (bend) due to expansion and contraction of the resin. However, this can be removed in this embodiment.
第１３図は本発明の第４実施例のガラスエポキシ等から
なる樹脂封止用回路基板の構成図であり、第１３図（ａ
）はその表面（半導体素子搭載面）図、第１３図（ｂ）
はその裏面（外部・続用端子面）図、第１４図は第１３
図の樹脂封止用回路基板に半導体素子を搭載し、モール
ド金型で挟んだ時の断面図を示している。FIG. 13 is a configuration diagram of a circuit board for resin sealing made of glass epoxy or the like according to a fourth embodiment of the present invention, and FIG.
) is its surface (semiconductor element mounting surface) view, Fig. 13(b)
Figure 14 is the back side (external/connection terminal side), and Figure 13 is the figure 14.
A cross-sectional view is shown when a semiconductor element is mounted on the resin-sealed circuit board shown in the figure and sandwiched between molds.
これらの図において、８１はガラスエポキシ基材、８２
、８６は配線パターン、８３．８３’は裏面接続用スル
ーホール、８４は外部接続用端子、８５は回路基板の表
面から上記スルーホール８３．８３′を介して枠に設け
られた測定用端子、９２は半導体素子、９３は半導体素
子９２と回路基板とを接続するワイヤ、９４はモールド
上金型、９５はモールド下金型である。In these figures, 81 is a glass epoxy base material, 82
, 86 is a wiring pattern, 83.83' is a through hole for connection on the back side, 84 is a terminal for external connection, 85 is a measurement terminal provided on the frame from the front surface of the circuit board through the through hole 83.83', 92 is a semiconductor element, 93 is a wire connecting the semiconductor element 92 and the circuit board, 94 is an upper mold, and 95 is a lower mold.
ここで、回路基板の外枠に配線パターン８２又は測定用
端子８５を設けることにより、基板表面の配線パターン
８２のメッキ厚による段差がなくなるため、モールド金
型９４．９５で基板を挟んでも局部的な圧力が加わるこ
とはない。このため、基板の配線パターン８２．８６に
モールド金型９４．９５の圧痕がつくこともない。By providing the wiring pattern 82 or the measurement terminal 85 on the outer frame of the circuit board, there is no difference in level due to the plating thickness of the wiring pattern 82 on the surface of the board, so even if the board is sandwiched between the molds 94 and 95, local No pressure will be applied. Therefore, there is no possibility that impressions of the molding die 94,95 will be made on the wiring patterns 82,86 of the board.
また、第１５図に示すように、測定用端子９６を樹脂封
止用回路基板の外枠の表面に形成するようにしてもよい
。Further, as shown in FIG. 15, the measurement terminals 96 may be formed on the surface of the outer frame of the resin-sealed circuit board.
第１６図は第１５図に示す樹脂封止用回路基板の外枠の
表面に測定用端子を形成し、これをモールド金型で挟ん
だ時の断面図である。FIG. 16 is a sectional view when measurement terminals are formed on the surface of the outer frame of the resin-sealed circuit board shown in FIG. 15, and this is sandwiched between molds.
この図に示すように、樹脂封止用回路基板の表面はフラ
ットになり、モールド金型９４．９５による局部的圧力
の発生はなくなるので、基板の外部接続用端子に金型の
圧痕は残らない。As shown in this figure, the surface of the circuit board for resin sealing becomes flat, and the local pressure caused by the molding die 94,95 disappears, so no mold impressions remain on the external connection terminals of the board. .
ここで、電気的特性の測定において、従来では、上記の
ように基板の外枠に設けた測定端子に、第１２図に示し
た測定用ポゴピンを接触させて測定していたが、本発明
によれば、基板の外部接続用端子にポゴピンを接触させ
る必要がないので、端子を傷つけることはなくなる。Here, in the measurement of electrical characteristics, conventionally, the measurement was carried out by bringing the measurement pogo pin shown in FIG. 12 into contact with the measurement terminal provided on the outer frame of the board as described above. According to this method, there is no need to bring the pogo pin into contact with the external connection terminal of the board, so the terminal is not damaged.
また、図示しないが、基板の下面の配線パターン以外の
箇所にダミー配線を形成するようにしてもよい。Further, although not shown, dummy wiring may be formed at a location other than the wiring pattern on the lower surface of the substrate.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、配線基
板の適切な箇所に保護膜を形成し、トランスファ成形を
行うようにしたので、以下の効果が得られる。(Effects of the Invention) As described above in detail, according to the present invention, a protective film is formed at an appropriate location on a wiring board and transfer molding is performed, so that the following effects can be obtained.
（１）基板をカード化した場合、カードとの密着性が向
上し、品質の向上及び安定化を図ることができる。(1) When the substrate is made into a card, the adhesion with the card is improved, and quality can be improved and stabilized.
（２）基板の貼り合わせかないため、基板の厚さを低減
できると共に、精度も良くなり、コストも安価になる。(2) Since the substrates are not bonded together, the thickness of the substrate can be reduced, accuracy is improved, and costs are reduced.
（３）保護膜がクンジョン材となり、かっ封止時におけ
る樹脂の流れ出しを防ぐことができる。(3) The protective film serves as a gunjong material, and can prevent resin from flowing out during sealing.
（４）金型の圧力による配線面への圧痕がなくなる。(4) There is no impression on the wiring surface due to the pressure of the mold.
（５）樹脂の注入口と略反対側に保護膜の切り離し部を
形成してエアーベントとしたので、ボイド等の発生を低
減し、安定した樹脂封止を行うことができる。(5) Since a cutaway portion of the protective film is formed on the side substantially opposite to the resin injection port to serve as an air vent, generation of voids etc. can be reduced and stable resin sealing can be performed.
更に、トランスファ成形用金型が、回路配線基板に形成
される導体パターンと、外枠に形成される測定用端子又
は導体パターンに当接するようにしたので、
（１）半導体素子面を樹脂封止する際、回路基板表面の
導体パターン部と外枠とのメッキ厚による段差がなくな
るため、金型の圧力による基板端子面への圧痕がなくな
る。Furthermore, since the transfer molding mold is in contact with the conductor pattern formed on the circuit wiring board and the measurement terminal or conductor pattern formed on the outer frame, (1) the semiconductor element surface is sealed with resin. When doing so, there is no difference in level due to the plating thickness between the conductor pattern portion on the surface of the circuit board and the outer frame, so there is no indentation on the board terminal surface due to the pressure of the mold.
（２）基板の外枠に設けた測定端子により電気的特性試
験等を行うことができるため、外部接続用端子が傷つく
ことがなくなる。(2) Since electrical characteristic tests can be performed using the measurement terminals provided on the outer frame of the board, external connection terminals will not be damaged.
第１図は本発明の第１実施例を示す樹脂封止用回路基板
の全体平面図、第２図はその樹脂封止用回路基板の構成
図、第３図は本発明の第１実施例を示す樹脂封止用回路
基板の製造工程図、第４図は従来の樹脂封止用回路基板
の製造工程図、第５図は第４図の（ｃ）工程詳細図、第
６図は第５図のＡ部拡大図、第７図はその樹脂封止用回
路基板の上面図、第８図は従来の他の樹脂封止用回路基
板の製造工程図、第９図は第８図のＢ部拡大図、第１０
図は本発明の第２実施例を示す樹脂封止用回路基板の構
成図、第１１図は本発明の第３実施例を示す樹脂封止用
回路基板の断面図、第１２図は従来の樹脂封止用回路基
板に半導体素子を搭載したＣ０Ｂ（チップ・オン・ボー
ド）の電気的測定状態断面図、第１３図は本発明の第４
実施例を示す樹脂封止用回路基板の構成図、第１４図は
第１３図の回路基板に半導体素子を搭載しモールド金型
で挟んだ時断面図、第１５図は本発明の第５実施例を示
す樹脂封止用回路基板の表面図、第１６図は第１５図の
回路基板に半導体素子を搭載しモールド金型で挟んだ時
の断面図である。
２１、４１．６０・・・配線基板部、２２．４２・・・
凹部、２３４３、６１．６２．８２．８６・・・配線パ
ターン、２４・・・リード端子、２５．５２．６３．９
２・・・半導体素子、２６．５３．６４９３・・・ワイ
ヤ、２７．５６．５６’・・・封止樹脂、３０．４８７
１・・・トランスファ成形用ゲート及びランナー部、３
１、４９．７２・・・金型のキャビティ周辺部、３２．
５０７２′・・・切り離し部、３３．４６・・・外枠、
４４．８３．８３’・・・スルーホール、４５・・・サ
ポートバー、４７．８７・・・保護膜（樹脂）、５１・
・・接着剤、５４．９５−・・下金型、５５゜９４・・
・上金型、８１・・・ガラスエポキシ基材、８４・・・
外部接続用端子、８５．９６・・・測定用端子。
特許出願人 沖電気工業株式会社
代理人 弁理士 清 水 守（外１名）１（橘≦Ｂ
月の％Ｉｉ’＞ヒ１メづの才【ｔＲ畜ｔｒｉヒ酵ン条〕
を末２〕リイト４１；？面Ｃづ第１図
オシ隆１ｔ１４１’ｌ’ｌ（＊ＪｔｔＮＨｔｔｆｆ）ｌ
Ｉ’１７トｔｉＪｅｊ％Ｑ第２図
１４ｆｆｉゴ２フ（Ｃ）ｘｔＴｉＹ＜ｖａ第５図
第
図
第
図FIG. 1 is an overall plan view of a resin-sealed circuit board showing a first embodiment of the present invention, FIG. 2 is a configuration diagram of the resin-sealed circuit board, and FIG. 3 is a first embodiment of the present invention. FIG. 4 is a manufacturing process diagram of a conventional resin-sealed circuit board, FIG. 5 is a detailed process diagram of (c) in FIG. 4, and FIG. Fig. 5 is an enlarged view of part A in Fig. 5, Fig. 7 is a top view of the resin-sealed circuit board, Fig. 8 is a manufacturing process diagram of another conventional resin-sealed circuit board, and Fig. 9 is the same as Fig. 8. Enlarged view of part B, No. 10
The figure is a configuration diagram of a circuit board for resin sealing showing a second embodiment of the present invention, FIG. 11 is a sectional view of a circuit board for resin sealing showing a third embodiment of the present invention, and FIG. 12 is a conventional FIG. 13 is a sectional view of an electrical measurement state of a C0B (chip on board) in which a semiconductor element is mounted on a circuit board for resin sealing, and is the fourth embodiment of the present invention.
A configuration diagram of a circuit board for resin sealing showing an embodiment, FIG. 14 is a cross-sectional view when a semiconductor element is mounted on the circuit board of FIG. 13 and sandwiched between molds, and FIG. 15 is a fifth embodiment of the present invention. FIG. 16 is a surface view of a circuit board for resin sealing showing an example, and is a sectional view when a semiconductor element is mounted on the circuit board of FIG. 15 and sandwiched between molds. 21, 41.60... Wiring board part, 22.42...
Recessed portion, 2343, 61.62.82.86... Wiring pattern, 24... Lead terminal, 25.52.63.9
2... Semiconductor element, 26.53.6493... Wire, 27.56.56'... Sealing resin, 30.487
1... Transfer molding gate and runner part, 3
1, 49.72...Mold cavity periphery, 32.
5072'... Separation part, 33.46... Outer frame,
44.83.83'... Through hole, 45... Support bar, 47.87... Protective film (resin), 51.
・・Adhesive, 54.95−・・Lower mold, 55°94・・
・Upper mold, 81...Glass epoxy base material, 84...
External connection terminal, 85.96... measurement terminal. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Mamoru Shimizu (1 other person) 1 (Tachibana≦B
%Ii' of the month
End 2] Reit 41;? Face Czu Figure 1 Oshiryu 1t141'l'l(*JttNHttff)l
I'17TotiJej%QFigure 214ffiGo2fu(C)xtTiY<vaFigure5FigureFigureFigure
Claims (6)
置し、サポートバーで支持される回路配線基板を連設し
、上面には保護膜がパターニングされ、トランスファ成
形により封止される樹脂封止用回路基板において、 前記回路配線基板のトランスファ成形用金型のキャビテ
ィ周辺部、トランスファ成形用ゲート及びランナー部並
びに前記外枠に、前記保護膜をパターニングすることを
特徴とする樹脂封止用回路基板。(1) Two outer frames arranged approximately parallel to each other, and a circuit wiring board positioned between the outer frames and supported by a support bar, are arranged in series, and a protective film is patterned on the upper surface, and is formed by transfer molding. In the resin-sealed circuit board to be sealed, the protective film is patterned on the peripheral part of the cavity of the transfer molding die of the circuit wiring board, the transfer molding gate and runner part, and the outer frame. Circuit board for resin sealing.
にしたことを特徴とする請求項１記載の樹脂封止用回路
基板。(2) The resin-sealed circuit board according to claim 1, wherein the width of the protective film is wider than the gate width.
保護膜に樹脂の注入口と略反対側に保護膜の切り離し部
を形成するようにしたことを特徴とする請求項１記載の
樹脂封止用回路基板。(3) The resin sealing device according to claim 1, wherein the protective film around the cavity of the transfer molding mold is formed with a cutaway portion of the protective film on a side substantially opposite to the resin injection port. circuit board.
置し、サポートバーで支持される回路配線基板を連設し
、上面には保護膜がパターニングされ、トランスファ成
形により封止される樹脂封止用回路基板において、 前記回路配線基板のトランスファ成形用金型のキャビテ
ィ周辺部、トランスファ成形用ゲート及びランナー部並
びに前記外枠、更に、前記回路配線基板の裏面の配線パ
ターン以外の箇所に、前記保護膜をパターニングするこ
とを特徴とする樹脂封止用回路基板。(4) Two outer frames arranged approximately in parallel, and a circuit wiring board positioned between the outer frames and supported by a support bar, are arranged in series, and a protective film is patterned on the upper surface, and is formed by transfer molding. In the resin-sealed circuit board to be sealed, the peripheral part of the cavity of the transfer molding die of the circuit wiring board, the transfer molding gate and runner part, the outer frame, and the wiring pattern on the back side of the circuit wiring board A circuit board for resin sealing, characterized in that the protective film is patterned in other locations.
置し、サポートバーで支持される回路配線基板を連設し
、トランスファ成形により封止される樹脂封止用回路基
板において、 （ａ）前記回路配線基板に形成される導体パターンと、 （ｂ）前記外枠に形成される測定用端子とを有し、（ｃ
）トランスファ成形用金型が前記導体パターン及び測定
用端子に当接することを特徴とする樹脂封止用回路基板
。(5) A resin-sealed circuit that is sealed by transfer molding, with two outer frames arranged approximately parallel to each other and a circuit wiring board positioned between the outer frames and supported by a support bar. The board includes (a) a conductive pattern formed on the circuit wiring board, (b) a measurement terminal formed on the outer frame, and (c)
) A circuit board for resin sealing, characterized in that a transfer molding die is in contact with the conductor pattern and the measurement terminal.
置し、サポートバーで支持される回路配線基板を連設し
、トランスファ成形により封止される樹脂封止用回路基
板において、 （ａ）前記回路配線基板に形成される第１の導体パター
ンと、 （ｂ）前記外枠に形成される第２の導体パターンとを有
し、 （ｃ）トランスファ成形用金型が前記第１及び第２の導
体パターンに当接することを特徴とする樹脂封止用回路
基板。(6) A resin-sealed circuit that includes two outer frames arranged approximately in parallel and a circuit wiring board positioned between the outer frames and supported by a support bar, and sealed by transfer molding. The board includes (a) a first conductive pattern formed on the circuit wiring board, (b) a second conductive pattern formed on the outer frame, and (c) a transfer molding die. A circuit board for resin sealing, characterized in that it comes into contact with the first and second conductor patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1243518A JP2596615B2 (en) | 1989-02-08 | 1989-09-21 | Circuit board for resin sealing |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-27385 | 1989-02-08 | ||
| JP2738589 | 1989-02-08 | ||
| JP1243518A JP2596615B2 (en) | 1989-02-08 | 1989-09-21 | Circuit board for resin sealing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH031560A true JPH031560A (en) | 1991-01-08 |
| JP2596615B2 JP2596615B2 (en) | 1997-04-02 |
Family
ID=26365299
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1243518A Expired - Fee Related JP2596615B2 (en) | 1989-02-08 | 1989-09-21 | Circuit board for resin sealing |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2596615B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0692820A1 (en) * | 1994-07-15 | 1996-01-17 | Shinko Electric Industries Co. Ltd. | Manufacturing one sided resin sealed semiconductor devices and a carrier used for it |
| EP0715348A3 (en) * | 1994-11-29 | 1998-07-15 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
| US5982625A (en) * | 1998-03-19 | 1999-11-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor packaging device |
| US6172424B1 (en) | 1996-10-11 | 2001-01-09 | Denso Corporation | Resin sealing type semiconductor device |
| US6333212B1 (en) | 1995-08-25 | 2001-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| EP0961317A3 (en) * | 1998-05-18 | 2002-07-24 | ST Assembly Test Services Limited | A method of encapsulating an electronic component |
| KR100857916B1 (en) * | 2008-01-22 | 2008-09-10 | (주) 지오시스 | Solidifying agent and method for solidfying soft ground using it |
| JP2011049253A (en) * | 2009-08-25 | 2011-03-10 | Stanley Electric Co Ltd | Led unit and method for manufacturing the same |
| JP2012235147A (en) * | 2006-06-09 | 2012-11-29 | Lg Electronics Inc | Light emitter package module |
-
1989
- 1989-09-21 JP JP1243518A patent/JP2596615B2/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0692820A1 (en) * | 1994-07-15 | 1996-01-17 | Shinko Electric Industries Co. Ltd. | Manufacturing one sided resin sealed semiconductor devices and a carrier used for it |
| US5732465A (en) * | 1994-07-15 | 1998-03-31 | Shinko Electric Industries Co., Ltd. | Method of manufacturing one side resin sealing type semiconductor devices |
| EP0715348A3 (en) * | 1994-11-29 | 1998-07-15 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
| US6333212B1 (en) | 1995-08-25 | 2001-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US6172424B1 (en) | 1996-10-11 | 2001-01-09 | Denso Corporation | Resin sealing type semiconductor device |
| US5982625A (en) * | 1998-03-19 | 1999-11-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor packaging device |
| EP0961317A3 (en) * | 1998-05-18 | 2002-07-24 | ST Assembly Test Services Limited | A method of encapsulating an electronic component |
| JP2012235147A (en) * | 2006-06-09 | 2012-11-29 | Lg Electronics Inc | Light emitter package module |
| JP2014195083A (en) * | 2006-06-09 | 2014-10-09 | Lg Electronics Inc | Light emitter package module |
| KR100857916B1 (en) * | 2008-01-22 | 2008-09-10 | (주) 지오시스 | Solidifying agent and method for solidfying soft ground using it |
| JP2011049253A (en) * | 2009-08-25 | 2011-03-10 | Stanley Electric Co Ltd | Led unit and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2596615B2 (en) | 1997-04-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |