JPH03150922A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To keep the signal delay constant over a wide temperature range by applying temperature correction to an output load of a semiconductor circuit to keep the signal delay constant. CONSTITUTION:A prescribed load capacitor C1 connects to a signal line 2 at the output side of a semiconductor circuit 1 being an object to temperature correction via a MOS TR 3 and a diode level V1 is applied to a gate of the MOS TR 3. The diode level V1 is a high level terminal voltage of diodes 4 connected in series of n-stage with a prescribed current flowing therethrough having a negative temperature coefficient. Then the gate level of the MOS TR 3 is controlled against a change in ambient temperature to control the load capacitor C1 connecting to the signal line 2 thereby applying temperature correction to the output load of the semiconductor circuit 1 and keeping the signal delay constant. Thus, the signal delay over a wide temperature range is kept constant.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a semiconductor integrated circuit device, and aims to provide a semiconductor integrated circuit device that can maintain a constant signal delay over a wide temperature range. A predetermined load capacitance is connected to the side signal line via a MOS transistor, and a diode potential is supplied to the gate of the MO1 transistor. The semiconductor circuit is Configure the output load to temperature compensate to keep signal delay constant.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a temperature cancellation function that suppresses temperature dependence of signal delay.

In recent years, various control signals have been used in semiconductor integrated circuits as speeds have increased.Generally, when the circuit has a CMO3 configuration, the signal delay tends to become shorter at low temperatures and longer at high temperatures. There is a need for a circuit design that takes such phenomena into consideration.For example, this corresponds to the design of an ATD circuit for an SRAM.

[Conventional technology]

In conventional semiconductor integrated circuit devices, no special circuit consideration is given to temperature changes, and the timing of the signals generally becomes faster at low temperatures, for example, when the circuit has a CMO3 configuration.

[Problem to be solved by the invention]

However, in such conventional semiconductor integrated circuit devices, when controlling signals within the circuit at high speed, the degree of signal delay changes with temperature changes, making it difficult to adjust timing over wide temperature changes. There was a problem in that this was a hindrance to speeding up the process.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device that can maintain a constant signal delay over a wide temperature range.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, a predetermined load capacitance C2 is connected to a signal vA2 on the output side of a semiconductor circuit l to be subjected to temperature correction via a MOS transistor 3 (for example, an N-channel type), and the M
O3) A diode potential VI is supplied to the gate of the transistor 3, and the diode potential V is set as the voltage at the high potential side end of n diodes 4 connected in series through which a constant current flows and which have a negative temperature coefficient. By controlling the gate potential of the transistor 3 (MO3) and controlling the load capacitance C6 transmitted to the signal line 2 with respect to changes in ambient temperature, the output load of the semiconductor circuit 1 is temperature-corrected and the signal is adjusted. Constructed to keep delay constant. In addition, 5 is a constant current source for causing a constant current to flow through the diode 4.

[Effect]

In the present invention, the potential V, - applied to the gate of the MO3I transistor 3 is the potential obtained by multiplying the voltage per stage of the diode 4 by the number of stages n (V+ = Vy x n), but the diode voltage ■, Since has a negative temperature coefficient, the gate potential of the MOS transistor 3 is low at high temperatures and high at low temperatures. Furthermore, the carrier mobility in the MoS transistor 3 has negative temperature dependence (gl increases at low temperatures).

Therefore, MO3I-transistor 3 has a load capacity N at high temperature.
It is easy to transmit cr to node B of signal line 2 (it becomes difficult to transmit at low temperature, and as a result, the output load of semiconductor circuit 1 is controlled so that it is small at high temperature and large at low temperature,
The delay in the signal output at high temperature is small and becomes large at low temperature. Therefore, the timing of the digital signal appearing at node B is constant over a wide temperature range.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

2 to 5 are diagrams showing an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a circuit diagram when the present invention is applied to an inverter. In this figure, 11 is an inverter corresponding to a semiconductor circuit to be subjected to temperature correction;
2 is a temperature cancellation circuit, and 13 is an inverter for waveform shaping.

Inverter 11 is a P-channel MO3I transistor 1
The digital signal input to the node A is inverted and transmitted to the temperature cancellation circuit 12 via a signal line 16. The temperature cancellation circuit 12 includes a first cancellation circuit 17 that corrects the signal delay in the lower half of the amplitude of the signal from the inverter 11 outputted to the signal line 16, and a first cancellation circuit 17 that corrects the signal delay in the upper half of the amplitude. The first cancellation circuit 17 is divided into a second cancellation circuit 18, and the first cancellation circuit 17 includes a predetermined load capacitance C1, an N-channel MO3) transistor 19 inserted between the signal line 16 and the load capacitance C1, and a constant current A P-channel MOS transistor 20 as a source and a diode having a negative temperature coefficient are connected in a y-stage series, and are inserted between the MOS transistor 20 and GND, and a diode potential ■1 is applied to the gate of MO3) transistor 19. It is composed of a diode group 21 that supplies .

The second cancellation circuit 1B includes a load capacitor Ct, a P-channel MO3) transistor 22 inserted between the signal line 16 and the load capacitor C2, and an N-channel MO3) transistor 23 as a constant current source. , connect the diodes in the X installation row, MO3I-transistor 23 and power supply ■. , and a diode group 24 which supplies a diode potential 2 to the gate of the MO3I transistor 22.

Both the first cancellation circuit 17 and the second cancellation circuit 18 control the gate potentials V, , V, of the MOS transistors 19.22 by diode groups 21.24, respectively, in response to changes in ambient temperature. By controlling the magnitude of the load capacitance ff1c+, cz transmitted to the inverter 16, the output load of the inverter 11 is temperature-compensated and the delay of the signal on the signal VA16 is kept constant. in particular,
By controlling the output load of the inverter 11 to be small at high temperatures and large at low temperatures, the delay of the output signal of the inverter 11 is made small at high temperatures and large at low temperatures, resulting in a constant signal delay. . Inverter 13
is composed of a P-channel MO3I-transistor 25 and an N-channel MO3I-transistor 26, and outputs the waveform-shaped signal while inverting the signal whose delay is kept constant as described above.

Next, the effect will be explained.

Each part shown in FIG. 2 is designated as a node A-E, and the voltages at each part are represented by 1 to 2. For ease of understanding, the temperature cancellation circuit 12 is divided into a first cancellation circuit 17 and a second cancellation circuit 18 and their functions are explained separately.The first cancellation circuit I7 is shown in FIG. Channel circuit 18 is shown in FIG.

First, paying attention to FIG. 3(a), the potential V applied to the gate of the MO3I transistor 19 is the potential (v+ -
However, since the diode potential (2) has a negative temperature coefficient, the gate potential (1) is low at high temperatures and high at low temperatures. To give a concrete example, if the junction temperature TJ of the diode is 0°C, VF = 0.9V, and y = 3 stages, then ■.

= 0.9X 3 = 2.7V. When the temperature rises to TJ-100'c, Vy = 0.7V, and V, = 0.7X3 = 2. It changes like lV. Therefore, for example, the threshold level V LhN of the MO3I transistor 19 is 1. If it is OV, then T1
When the temperature is -0°C, until either the potential of node B (5) or the potential (3) of node D rises to 1.7 V (VS≦
■1Vzl, H or V3 ≦V+ VthN) MO
S transistor 19 is in the on state, and at this time 9,
A load capacitor C1 is connected to the signal line 16 via an MO3I transistor 19. Then, when the potential 5 of the node B or the potential 5 of the node D becomes 1.7 V or more, the MOS transistor 19 is turned off, and the load capacitance C for the signal line 16 is turned off.
1 connection is broken.

The waveforms of each part based on the above action are shown as shown in FIG. 3(b). The signal at node A is inverted by the inverter 11 and output from the signal line 16, and when the signal at node B rises, unless the condition of V3≧VI-vL1,9 is satisfied, the MO3I-transistor 19 is turned on and the load capacity ffi is
Since c + is connected to the signal line 16, the load capacitance CI
The delay is effected by the capacitance of , so that the voltage rises slowly, and when the above condition is met, the connection of the load capacitor CI is cut off, so that the voltage rises rapidly. At this time, if the threshold level of the inverter 13 is VLh13, the potential 2 at the node B is high, and when it exceeds 3, the signal at the node C is inverted. Therefore, a signal delay (delay portion) as shown in the figure occurs. On the other hand, when the potential V of node B falls from a high level, if the conditions ≧V, -V are no longer satisfied, the load capacitance C1 is connected to the signal line 16, and the capacitance becomes effective, so the potential V gradually falls, and when it crosses 3 during the fall, the signal at node C is inverted.

Next, the processing of the upper half of the signal amplitude of node B is shown in Fig. 4 (a
), and if the threshold level of the MOS transistor 22 is v thr, the signal at node B rises. Hvs≦V2 V
While the condition of thl' is satisfied, the MOS transistor 22 is turned off and the connection of the load capacitor C2 to the signal line 16 is cut off, so the voltage rises rapidly, and when the above condition is no longer satisfied, the MOS transistor 22 is turned on and the load capacitor C2 is connected to the signal line 16, so the load capacitor C2 is connected to the signal line 16.
Due to the capacity of 2, the delay is effective and the rise is gradual. At this time, the potential V5 is V6. When the value exceeds 0, the signal at node C is inverted, and a delay component as shown in the figure occurs.

On the other hand, when the potential 5 of node B falls from a high level, the load capacitance Mcz is connected to the signal line 16 and the potential decreases as long as the condition of V4≦V2-V is not satisfied. 3.V is gradually falling and is falling while it is falling.3. , the signal at node C is inverted.

Combining the effects of both Figures 3 and 4 above, the 5th
As shown in the figure, as a result, the delay is effective over the entire range of VCC and GND, which are binary levels, and this delay is small at high temperatures and large at low temperatures. Therefore, the delay timing of the digital signal appearing at node C can be made constant over a wide temperature range. Therefore, it is possible to adjust the signal timing over a particularly wide temperature range, and by using this circuit, it is possible to increase the speed of the device.

In the above embodiment, the semiconductor circuit to be subjected to temperature correction is an inverter, but the present invention is not limited to this and can of course be applied to other digital signal circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIGS. 2 to 5 are diagrams showing an embodiment of a semiconductor integrated circuit device according to the present invention, FIG. 2 is an overall circuit diagram thereof, and FIG. 3 is a diagram thereof. FIG. 4 is a diagram explaining the operation of the first cancel circuit, FIG. 4 is a diagram explaining the operation of the second cancel circuit, and FIG. 5 is a waveform diagram of the operation of the entire circuit. 1...Semiconductor circuit, 2.16...Signal line, 3.19.22...MO3I-transistor, 4
... Diode, 5 ... Constant current source, 11 ... Inverter (semiconductor circuit), 12 ...
...Temperature cancellation circuit, 13...Inverter, 14.15.25.26...MO3I-transistor, 17...First cancellation circuit, 18.
...Second cancellation circuit, 19.22...
・・MOS transistor, 20.23・・・・・・MO
S) transistor (constant current source) 2I, 24... diode group, 22. 23...MOS transistor. GND Diagram for explaining the principles of the present invention --- 11 Plow -- Vio -- Kasumi --, --- J・12 Overall circuit diagram of one embodiment FIG. 2 GND FIG. Figure 4 explains the operation of the second cancellation circuit.

Claims (1)

[Claims] A predetermined load capacitance is connected to a signal line on the output side of a semiconductor circuit to be subjected to temperature correction via a MOS transistor, a diode potential is supplied to the gate of the MOS transistor, and the diode potential is , n stages of diodes through which a constant current flows and which have a negative temperature coefficient are connected in series, and a voltage is set at the high-potential end of the diodes, and the gate potential of the MOS transistor is controlled in response to changes in ambient temperature. 1. A semiconductor integrated circuit device, characterized in that the output load of the semiconductor circuit is temperature-compensated to maintain a constant signal delay by controlling a load capacitance transmitted to a signal line.