JPH03143228A - Power supply device - Google Patents

Abstract

PURPOSE:To supply a high-voltage power supply having desired waveforms in response to the characteristics of load by controlling conduction and interruption on the primary side in response to the switching currents of a switch circuit on the secondary side of a transformer. CONSTITUTION:The rectifying output V0 of a transformer T1 is voltage-divided at a specified ratio, and compared with reference voltage. When output voltage V0 reaches a specified value V1, a comparator 6 is inverted at a high level, and a transistor (TR)Q1 is interrupted. On the other hand, an output from the comparator 6 is also input to a delay circuit 41, is delayed only by a fixed value and short-circuits a TRQ41. An output at a time when the TRQ41 is interrupted is input to a PWM circuit 43, and TRs Q3, Q1 are driven. On the other hand, an output from a load current detector 48 is input to a comparator 47. When load is short-circuited, the comparator 47 is inverted at a high level, and the TRs Q2, Q1 are interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply device, and particularly to a power supply device that outputs a high voltage in which alternating current and direct current are superimposed.

[Prior Art] Conventionally, various electrophotographic image forming apparatuses have been used as image forming mechanisms of printers or copying machines. In an electrophotographic image Jf forming apparatus, loads such as a charger and a developing device that require a high voltage power supply are used.

Since the voltage required for each high-voltage load and the control method depending on the progress of the image forming sequence are different for each load, these power supply devices are controlled by different independent control structures.

In particular, the developing bias power source of the developing device is often composed of a step-up transformer for low-frequency AC output, and a DC-DC inverter coupled to the transformer to superimpose a DC voltage on the AC output. .

[Problems to be Solved by the Invention] In the conventional structure of the developing bias power supply described above, the step-up transformer for low frequency AC is large, and noise is generated because it is in the audible band, and it is difficult to reduce this. It is very difficult to do so, and even if one attempts to change the duty ratio by more than 50%, it is impossible due to the biased magnetization of the transformer. In addition, since the load is a capacitive load and rapid charging is difficult, there are problems such as the inability to increase the pulse rise speed.

In view of the above problems, conventional configurations as shown in FIGS. 7 and 8 are known. FIG. 8 shows signal waveforms at various parts of the circuit shown in FIG. In FIG. 7, symbols l and 2 are oscillators that generate constant pressure alternating current of rectangular waves, and the oscillator l
is a square wave with a frequency of 1800Hz and a duty ratio of 20% (
FIG. 8(A)), and the oscillator 2 has a frequency of 50 k,
I-1z, square wave with a duty ratio of 50% (Figure 8 (B)
waveform part).

The output of the oscillator 2 is input to the modulator 3, and is almost 100% modulated by the output signal of the oscillator 2 to obtain the waveform shown in FIG. 8(B). The modulation circuit 3 supplies a constant voltage power supply voltage +Vc to the primary winding of the step-up transformer TI via the transistor Ql.
Control the application of c.

On the secondary side of the transformer TI, a rectifying diode D1.
A clamp circuit for superimposing a DC component, which includes a large-capacity capacitor CI, a diode D2, and a DC power source 5 (output -VE), is connected via a discharge resistor R1. The clamp output is output from the terminal P1 to the developing device as a developing bias. Further, the connection point between the resistor R1 and the clamp capacitor c1 can be grounded by a switch 4 consisting of a relay, an analog switch, or the like.

Note that the connection method of the transformer TI and diode DI is a flyback method as shown in the figure. As shown in FIG. 8(C), the switch circuit 4 becomes conductive in synchronization with the low level output of the oscillator 1, that is, the cutoff of the transistor Q1 and the transformer TI. Transistor Q1 is 50kHz
During the period when it is driven by z, the clamping diode D
A voltage of 10v1 is obtained at the cathode of I, and is smoothed by the clamping capacitor C1, so that the output of the switch circuit 4 becomes as shown in FIG. 8(C). The power supply output obtained in this way is connected to the output terminal PI via the clamping capacitor C2, but the clamping diode D2 conducts at the peak timing in the positive direction and is connected to the DC power supply 5 having an output of -VE. Since the output is clamped, an output whose peak value in the positive direction is -VE is obtained as shown in FIG. 8(D). As is clear from FIG. 8(D), this output is a superposition of the negative DC voltage -VE and the rectangular wave AC of 1800 Hz voltage 1.

According to the above configuration, since the transformer TI itself is driven at a high frequency, there is no need to use a large transformer that can be driven at a low frequency as in the past, the power supply section can be configured to be small and lightweight, and noise countermeasures can be easily implemented. There is an advantage.

However, in the conventional configuration described above, the load is the developing roller of the developing device, and this developing roller is a capacitive load whose majority is the capacitance between it and the opposing photosensitive drum surface. As shown, there is a problem in that the rise is considerably slower than that of the output waveform (FIG. 9(A)) when forward resistance is used as the load.

An object of the present invention is to solve the above problems and provide a power supply device that can supply high-voltage power with a desired waveform depending on the characteristics of the load.

[Means for Solving the Problems J] In order to solve the above problems, in the present invention, in a power supply device that outputs high voltage in which alternating current and direct current are superimposed,
a low-frequency oscillator, a high-frequency oscillator, a transformer whose primary side low-voltage direct current input is controlled according to one of the outputs of these oscillators depending on the output voltage, a rectifier that rectifies the output of this transformer, and a switch means for connecting and disconnecting between the output point of the rectifier and the ground potential in synchronization with the output signal of the low frequency oscillator; a means inserted between the switch means and the ground potential for detecting a switch current; means for energizing the L secondary side of the transformer and cutting off the switch means during a period in which the detected switch current exceeds a predetermined value; We adopted a configuration consisting of a clamp circuit that clamps power to the level and then supplies power to the load.

[Function] According to the above configuration, the load current at the time of a load short circuit can be reduced even when power is being supplied to a capacitive load by controlling the energization cutoff on the primary side according to the switch current of the switch circuit on the secondary side of the transformer. Can be reduced.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings.

FIG. 1 shows the configuration of a power supply device employing the present invention. In FIG. 1, the same reference numerals are used for the same members as in the conventional example shown in FIG.

The major difference from the conventional example in FIG. 7 is that the high frequency oscillation circuit 2 in FIG. 7 is replaced with a PWM circuit 43 (frequency f2) (the frequency of oscillator I is i't), and The point is that a plurality of control systems consisting of a comparator 6.47 and a delay circuit 17.4I are added in order to control the operation of the l transistor Ql that drives the side.

Further, the switch circuit 4 in FIG. 1 is composed of a high voltage transistor Q2.

The embodiment shown in FIG. 1 has a drawback in the conventional configuration shown in FIG. 7, that is, the capacitive load is mostly the capacitance between the developing roller and the opposing photosensitive drum surface, so the embodiment shown in FIG. This is to overcome the problem of slow rise, and increases the charging voltage of the load capacitor, that is, the rectified output vO, and speeds up the charging time constant to speed up the output rise.
The power supply to the primary side of the transformer T1 is cut off when the output reaches a predetermined level.

It also aims to protect the circuit in the event of a load short circuit, which has not been considered in the conventional example.

The configuration shown in FIG. 1 will be described in detail below.

The base of the transistor Ql that drives the primary side of the transformer Tl is controlled by the transistor Q3 or Q42. The base of transistor Q3 is connected to diode D41.
It is controlled by the level of the higher voltage among the outputs of the comparator 6, oscillator 1, or PWM circuit 43 via D42 and D43.

The half-wave rectified output by the capacitor C5 and diode D6 of the secondary side output of the transformer TI is output by the diode D1. Resistance R1
It is connected to the collector of the transistor Q2 constituting the switch circuit 4 (the collector potential is 0) via the transistor Q2. Transistor Q2 is driven by the output of oscillator l.

Further, the corefthal emitter of a transistor Q41 is connected between the base of the transistor Q2 and the ground, and the base of the transistor Q41 is driven by the output of the comparator 47 via a diode D46.

Further, a load current detection circuit 48 is inserted between the emitter and ground of the transistor Q2. Capacitor C42 is an integrating capacitor, and transistor Q2 under normal load.
Smoothes the pulse component at short conduction timing.

The comparator 47 detects the emitter current of the transistor Q2 via the detection circuit 48, compares it with a reference voltage obtained by dividing the power supply voltage VCC at a predetermined voltage division ratio, and outputs the difference voltage.

Further, the output of comparator 47 controls the base of transistor Q42 via diode D45.

The collector potential vO1 of the transistor Q2, that is, the voltage value corresponding to the output voltage, is divided by resistors R41 and R42, further divided by resistors R41' and R42', and inputted to the comparator 6. The comparator 6 compares this input voltage with a control voltage input from a control system (not shown) via the terminal P2, and outputs a difference voltage.

0 The output of the comparator 6 is input to the transistor Q3 via the diode D41, and after being delayed by the delay circuit 41, controls the base of the transistor Q41. The delay circuit 41 turns on or off the transistor Q41, so that the collector of the transistor Q41 controls the input terminal of the voltage follower 42 to one of two voltages described below. The voltage follower 42 transmits these voltage values as they are to the PWM circuit 43 and inputs them to the PWM circuit 43 manually. The delay circuit 41 and voltage follower 42 have the same functions as the modulation circuit shown in FIG.

The PWM circuit 43 controls the output pulse width according to the input voltage.

Note that C41 in FIG. 1 indicates the load capacity of the developing roller in the case of an image forming apparatus. In addition, in Fig. 1 (or Figs. 3, 5, and 6 described later), the capacitor C
The illustration of the clamp circuit (see FIG. 7) connected after 1 is omitted.

Figures 2 (A) to (C) show the operation of the circuit in Figure 1. A waveform diagram is shown.

When the power supply voltage vCC is applied to each application point in FIG. 1 and a control voltage corresponding to a predetermined output voltage is input to the terminal P2, the circuit in FIG. 1 starts supplying power to the load.

The rectified output v port of the transformer TI is divided into voltages at a predetermined ratio by resistors R41 and R42, and the input terminal P2 is input to the comparator 6.
is compared with the reference voltage input to the

When the output voltage VO reaches the predetermined value v1, the comparator 6
is reversed from low level to high level. This output makes diode D41 conductive, turns on transistor Q3, sets the base of transistor Q1 to zero potential, and cuts off transistor Ql.

That is, each time the output vO divides the control voltage of the comparator 6, the transistor Ql turns on (Fig. 2(B),
(C)), the output voltage Vl is maintained, and as shown in FIG. 2(A), the rise of the output vO is significantly improved. The V port shown in FIG. 2(A) is the saturation value of the rectified output. In addition,
Output ■0 of 2 To reduce overshoot and ripple,
Comparator 6 must be sufficiently fast.

On the other hand, the output of the comparator 6 is also input to the delay circuit 41 and is delayed by a predetermined value TI which is larger than the period 1/f2 and sufficiently smaller than l/fl, and short-circuits the transistor Q41 only during T1. When the transistor Q41 of the voltage follower 42 is cut off, the output is 44 Vcc.
・(1) R44+R43.

This output is manually input to the PWM circuit 43 of frequency f2,
Transistor Q3 with a pulse width according to the voltage in equation (1),
Drive Ql. When the output vo reaches vl, the comparator 6 and the delay circuit 41 operate to turn on the transistor Q41 for Tl, and the output of the voltage follower 42 becomes 44 45 .

Therefore, the pulse width of the output of the PWM circuit 43 becomes shorter,
Even if the comparator 6 is turned off again, the charging speed of the load capacitor C41 becomes slower.

On the other hand, the output of the load current detection circuit 48 is
7 is input. When the load is short-circuited, use a large capacity capacitor C1.
are charged, the energization timing of transistor Q2 becomes longer, the detection voltage increases, and comparator 47 is inverted from low level to high level, and transistors Q41.
Transistors Q2 and Ql are respectively cut off via C42.

This reduces the load current when the load is short-circuited, making it possible to protect the circuit elements.

The configuration of FIG. 1 can be modified as shown in FIGS. 3 to 6.

In FIG. 3, instead of providing a delay circuit, the charging speed of the load capacitor C41 is slowed down so that the output vO reaches the level v2 immediately before reaching the final level vI. The comparator 6 detects the final level Vl and completely cuts off the primary side current supply, just as in the embodiment shown in FIG. The comparator 61 operates at a level v2 set slightly lower than vl, turns on the transistor Q41, reduces the amount of current on the primary side, and slows down the charging speed of the load capacitor C41.

FIG. 4 shows an example in which the output vO is supplied to the sleeve of the developing device via the DC superimposition circuit and the high-frequency cut filter 72. The DC superimposition circuit includes a rectifier diode D71. It is composed of a smoothing capacitor C71, an operational amplifier 71, and a high voltage transistor Q71.

A part of the secondary output of the transformer TI is fed to the DC superimposition circuit via the resistor R74. The rectified output of the diode D71 is input to the comparator 71 through a voltage dividing circuit of resistors R71 and R72, and is compared with the reference voltage input to the terminal P4, and the collector current of the transistor Q71 is controlled to stabilize it at a predetermined times 5 of the reference voltage. be converted into As a result, the DC component is controlled at a constant voltage.

A rectified output from a diode D71 is superimposed on the AC output vO by a capacitor Ct and a resistor R73. This output is processed by a high-frequency cut filter 72 composed of an impedance element and a load capacitance C41 to generate a high frequency f2.
ripple is removed. As the high-frequency cut filter 72, a choke coil or a resistor can be used.

Note that in FIGS. 3 and 4, the transistor Q is shown for simplification.
2 emitter circuit and a control system using a comparator 47 (
(see Figure 1) are omitted.

In FIG. 5, a resistor R47 is connected to the output of the output comparison comparator 47 of the load current detection circuit of the embodiment shown in FIG. 1 to form a hysteresis comparator.

FIG. 6 shows the output of the output comparison comparator 47 of the load current detection circuit of the embodiment shown in FIG.
and delayed by capacitor C43, transistor Q1. The cut-off period of Q2 is maintained for a predetermined period of time.

According to each of the above embodiments, the following effects can be obtained.

(1) There is no need to use a low-frequency transformer, resulting in significant downsizing, cost reduction, and improved reliability.

(2) For the same reason as (1), audible noise can be completely eliminated.

(3) It is possible to freely set the duty ratio of AC output other than 50%, which was previously impossible, and it is also possible to use a desired duty ratio.

(4) AC amplitude can be stabilized very easily.

(5) According to the configuration shown in Fig. 4, a part of the amplitude-stabilized output is voltage-doubled and rectified to obtain the clamping power source.
The clamp power supply itself is also stabilized. Therefore, stable outputs in both amplitude and DC level can be easily obtained.

(6) Power cutoff on the primary side is controlled according to the switch current of the switch circuit on the secondary side of the transformer, and the rise speed of the AC output is significantly improved, so the load is reduced to less than 7 In this case, development efficiency can be increased, recording density can be improved, and density stabilization can be expected.

(7) Output amplitude can be stabilized with high precision.

(8) By using a high-speed element for the comparator 6, overshoot and high frequency ripple can be eliminated.

(9) Also, by reducing overshoot and high frequency ripple, the high voltage transistor Q that drives the secondary side
2 collector voltage can be lowered, and cheaper elements can be used.

(10) Load short-circuit current can be suppressed to a predetermined value or less, and circuit elements can be protected.

(11) In particular, according to the embodiments shown in FIGS. 5 and 6, when the load short-circuit current exceeds a predetermined value, a certain cut-off time can be ensured, so that safety for the load is ensured, and at the same time,
Temperature rise of circuit elements can be suppressed.

Although the developing device of the image forming apparatus has been considered as a load in the above, a similar configuration can be implemented for AC/DC superimposed output to other loads, especially capacitive loads.

[Effects of the Invention J As is clear from the above, according to the present invention, in a power supply device that outputs a high voltage in which alternating current and direct current are superimposed, a low frequency oscillator, a high frequency oscillator, and a a transformer whose primary side low-voltage DC input is controlled according to one of the outputs of the transformer, a rectifier that rectifies the output of the transformer, and an output signal of the low-frequency oscillator that is connected between the output point of the rectifier and ground potential. a switch means for detecting a switch current, which is inserted between the switch means and the ground potential, and a switch means for detecting a switch current detected by the detecting means; A configuration is adopted that includes means for energizing the primary side and interrupting the switch means, and a clamp circuit that clamps the AC voltage generated at the connection point between the switch means and the rectifier to a predetermined DC level and then supplies power to the load. Therefore, by controlling power cutoff on the primary side according to the switch current 9 of the switch circuit on the secondary side of the transformer, it is possible to reduce the load current at the time of a load short circuit and protect the circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of a power supply device adopting the present invention, Figs. 2 (A) to (C) are power waveform diagrams showing the operation of the device in Fig. 1, and Figs. 3 to 6 The figures are circuit diagrams showing other embodiments of the present invention, FIG. 7 is a circuit diagram showing the configuration of a conventional device, and FIGS. 8(A) to (D) are power waveform diagrams of each part of FIG. 7. 9(A) and 9(B) are enlarged views of the output waveform of FIG. 7. l, 2...Oscillator 3...Modulation circuit 4-...Switch circuit 6.47
．． 61.71... Comparator 41... Delay circuit
42-...Voltage follower 43...-PWM circuit 72-...High frequency cut filter TI...Transformer 0

Claims (1)

[Claims] 1) A power supply device that outputs a high voltage in which alternating current and direct current are superimposed, including a low frequency oscillator, a high frequency oscillator, and a primary-side power source according to the output of one of these oscillators depending on the output voltage. a transformer that controls a low-voltage DC input; a rectifier that rectifies the output of the transformer; a switch that connects and connects the output point of the rectifier to ground potential in synchronization with the output signal of the low-frequency oscillator; A means for detecting a switch current, which is inserted between the switch means and the ground potential; What is claimed is: 1. A power supply device comprising: means for cutting off; and a clamp circuit that clamps an AC voltage generated at a connection point between the switch means and the rectifier to a predetermined DC level and then supplies power to a load. 2) The power supply device according to claim 1, wherein the energization cutoff control of the energization cutoff means has a predetermined hysteresis characteristic or delay characteristic.