JPH03136176A - Pulse signal generating system - Google Patents

Abstract

PURPOSE:To easily obtain a pulse signal which has the period determined with an arbitrary reduction rate by masking a reference clock signal with the signal indicating the presence or the absence of carry at the time of addition of the fraction part of a numerical value indicating the reduction rate. CONSTITUTION:A fraction part to set the reduction rate and the fraction part of the addition result are added by an adding means 13, and the reference clock signal is masked with the signal indicating the presence or the absence of carry by a mask means 14, and the pulse signal having the period determined by the set reduction rate is obtained. Since the reduction rate is arbitrary set, the reduction rate is easily changed. Thus, the pulse signal having the period determined by the arbitrary reduction rate is easily obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a pulse signal generation method having a period determined by a desired reduction rate compared to a reference clock signal, the present invention indicates the presence or absence of a carry when adding a decimal fraction of a numerical value indicating a reduction rate. The purpose is to easily obtain a pulse signal with a period determined by an arbitrary reduction rate by masking the reference clock signal with a signal, and a positive number (decimal part) less than 1 is used for setting the reduction rate. When the adder is prepared and performs an addition operation sequentially in synchronization with a reference clock signal, the decimal part of the addition result is added to the positive number less than 1, and the presence or absence of a carry obtained during the addition operation is indicated. The reference clock signal is masked by a masking means according to the signal, and a pulse signal having a period determined by the reduction rate is generated.

(Industrial Application Field) The present invention relates to a pulse signal generation method having a period determined by a desired reduction ratio compared to a reference clock signal.

(Prior Art) When serially outputting a digital image, the original image data is reduced by reducing the number of times a clock (transfer lock) synchronized with the image data is generated. Since the reduction ratio is not fixed and various reduction ratios are required depending on the user, it is necessary to generate thinning pulses with arbitrary reduction ratios using an inexpensive method.

As shown in Figure 4, the conventional pixel density conversion pulse generation method consists of a counter 1 that uses the reference clock as a coefficient, a memory 2 that transfers and locks the memory output using the counter output as an address, and a memory 2 that uses the counter output as an address to transfer and lock the memory output. It consists of an OR circuit 3 that outputs a logical sum. For example, when reducing the size to 1/4, it is only necessary to output the transfer lock once for every 4 times of the reference clock, so the memory address is 4 times.
Write O to addresses that are multiples of , and 1 to other addresses, and the address data that is input to memory 2 is a coefficient of the reference clock in sequence, so the memory output is once for every 4 reference clocks. Output 0 at the rate of
The OR circuit 3 outputs the logical sum with the reference clock as 1/4 of the reference clock.

[Problem to be solved by the invention]

In the conventional pixel density conversion pulse generation method described above, the reduction ratio is set in the memory 2 in advance, so it is not versatile, and in order to have versatility, many thinning pulse generation patterns must be registered. There was a problem in that it required a large amount of memory capacity and hardware.

The present invention has been made in view of the above problems, and the technical problem set for the purpose of solving the problem is to use a signal indicating whether or not there is a carry when adding the decimals of the numerical value indicating the reduction rate. It is an object of the present invention to provide a pulse signal generation method which makes it possible to easily obtain a pulse signal having a period determined by an arbitrary reduction ratio by masking a reference clock signal.

[Means to solve the problem]

As a specific means for solving the above-mentioned problems, the present invention, in configuring a pulse signal generation method, uses a positive number (decimal part) less than 1 as a reduction ratio, as shown in the principle diagram of FIG. During the addition operation in the addition means 13 prepared for setting and performed sequentially in synchronization with the reference clock signal,
The decimal part of the addition result and the positive number less than 1 are added, and the reference clock signal is masked by the masking means 14 using a signal indicating the presence or absence of a carry obtained during the addition operation, and the cycle is determined by the reduction rate. It was decided to generate a pulse signal having .

[Effect]

With the above configuration, the present invention adds the decimal part for setting the reduction rate and the decimal part of the addition result by the addition means 13, masks the reference clock signal by the masking means 14 with a signal indicating the presence or absence of carry, and sets the reduction rate. A pulse signal having a period determined by the reduction ratio obtained is obtained. Since the reduction rate can be set arbitrarily, the reduction rate can be easily changed.

(Example) Hereinafter, a case where the reduction ratio is 1/4 will be illustrated and explained as an example of the present invention.

A block diagram of the configuration according to the embodiment is shown in FIG. 2(a). Here, 21 is a setting register that sets and stores the reduction rate in binary; for example, Hc374 or Ls374.
It is constructed using an integrated circuit having a serial number of 2 bits, and stores rob and rlJ, respectively, as shown in the figure.

Reference numeral 22 denotes an addition register for storing the addition result as addition data for the next addition, which is constructed using, for example, Hc374 or Ls374, and has 2 bits as shown. 23 is the output of the setting register 21 and the addition register 2
2 and outputs a carry signal when there is a carry, for example, Hc28.
It is constructed using an integrated circuit having a serial number of 3.

24 is an inverter circuit that inverts and outputs the carry signal. 25 is an OR circuit that transfers the logical sum of the output of the inverter circuit 24 and the reference clock and outputs it as a lock.

When generating pulses from the reference clock at a reduction rate of 1/4 using the embodiment configured as described above, first, the setting value 1/4 = 0.25, specifically 2, is set in the setting register 21.
When the base number 01 is set and activated, the output of the first adder 23 is as shown in FIG. is stored in Addition register 22
When stored in the adder 2, the stored contents are immediately stored in the adder 2.
3 and is added to the contents of the setting register 21 at the next rising edge of the reference clock signal, as shown below the reference clock waveform in FIG.

Then, the output of the adder 23 is outputted by adding the contents of the addition register 22 and the contents of the setting register 21 and stored in the addition register 22.

When the output of the adder 23 is stored in the addition register 22,
Each time, the accumulated value corresponding to the contents of the setting register 21 is stored.

When the output of the adder 23 becomes 1, a carry signal is output from the adder 23, and the value stored in the addition register 22 becomes O.
become. In other words, as shown in the table, the decimal part of the addition result is r
OJ (00), and this value rOJ is stored in the addition register 22.

Such a calculation process is repeated, and as shown in the table, the adder 23 periodically outputs a carry signal once every four times.

The carry signal output from the adder 23 is inverted by the inverter circuit 24 and input to the OR circuit 25.

The OR circuit 25 calculates the logical sum of the inverted value of the carry signal and the reference clock, and outputs a one-pulse pulse signal every four reference clocks.

In this embodiment, the carry signal is output at a proportion commensurate with the reduction rate by setting the binary reduction rate value in the setting register 21, so that the output of the OR circuit 25 It is also possible to output one pulse signal every four reference clocks at a similar rate.

FIG. 2(b) is a configuration diagram of another embodiment of the present invention.
Parts equivalent to those in Figure (a) are given the same reference numerals. This second
In the figure (b), 26 is a multiplexer, which uses the carry signal from the adder 23 as a selection signal, and
The [all H (all high)] signal and the reference clock are input signals, and the signal indicating the presence or absence of a carry is H (high) [carry present; when the carry signal is KO, the reference clock is output from the multiplexer 26, When the signal indicating the presence or absence of a carry is L (low) [no carry], the multiplexer 26
As a result, an all-H signal is output from the multiplexer 26, and a pulse signal having the same waveform as the output of the OR circuit shown in FIG. 3 is obtained from the multiplexer 26.

Note that the present invention is not limited to the above embodiments,
Any circuit that masks the reference clock with a signal indicating whether there is a carry from the adder 23 (a combinational circuit of logic gates)
You may also use

In this way, the reduction ratio can be easily changed by changing the contents of the setting register 21, and a pulse having a period determined by an arbitrary reduction ratio can be generated using a versatile device without increasing the amount of hardware. I can get a signal.

〔Effect of the invention 〕

As described above, in the present invention, the reduction ratio can be easily changed by changing the numerical value for setting the reduction ratio, and the reciprocal of the reduction ratio is increased by 1 based on the result of addition based on the set reduction ratio.
A pulse signal having a period determined by the reduction ratio can be obtained by masking the reference clock signal using a signal indicating the presence or absence of a carry, including a carry signal output at a rate of 1.

If the present invention is applied to pixel density conversion, the pixel density can be converted at an arbitrary reduction rate, the memory capacity is small, and the hardware is required.

As a result, a device that digitally handles image information can be realized at low cost as a simplified device that can easily perform scale conversion.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the pulse signal generation method according to the present invention. FIG. 2(a) is a configuration diagram of an embodiment of the present invention. FIG. 2(b)
3 is a configuration diagram of another embodiment of the present invention, FIG. 3 is a timing chart according to the embodiment, and FIG. 4 is a configuration diagram showing a conventional example. 13...Addition means 14...Mask means

Claims (1)

[Claims] A positive number (decimal part) less than 1 is prepared for setting the reduction rate, and when the adding means (13) sequentially performs the addition operation in synchronization with the reference clock signal, the decimal part of the addition result and the number less than 1 are the reference clock signal is masked by a masking means (14) using a signal indicating the presence or absence of a carry obtained during the addition operation, and a pulse signal having a period determined by the reduction ratio is generated. Characteristic pulse signal generation method.