JPH03135244A - Phase synchronous method - Google Patents

Abstract

PURPOSE:To decide a delay quantity at high speed by detecting a delay difference in a delay difference detection control means and setting the phases of channels which are returned through respective terminal equipments (TE) by means of setting the detected difference to be the delay quantity of a variable delay means to be coincident. CONSTITUTION:A network terminal equipment (NT) 10 sequentially designates TE which adjust delay and designated TE inputs a training pattern from a pattern transmission means 12 to the delay difference detection control means 15 through a delay means 14 having an open-loop delay quantity when TEn connected in the longest distance. The training pattern from the pattern transmission means 12 is transmitted to NT 10 through the variable delay means 13 and is inputted to the delay difference detection control means 15 of TE1 in a loop back means 11. The delay difference detection control means 15 detects the delay difference of both inputs and sets the detected delay difference to be the delay quantity of the variable delay means 13. Thus, the delay quantity of the variable delay means 13 can be decided by one transmission of the training pattern.

Description

[Detailed Description of the Invention] (Summary) This invention relates to a phase synchronization method for a communication system using a multiple access control method in which a network terminal device (hereinafter referred to as NT) and a plurality of terminal devices (hereinafter referred to as TE) are connected via a bus. , In order to provide a phase synchronization method that can quickly determine the amount of delay in the variable delay section in the TE, the NT is provided with a loopback means for looping back signals from the upstream line of the bus to the downstream line of the bus. Each TE also includes a pattern sending means for sending out a training pattern, a variable delay means for inputting the output of the pattern sending means and capable of varying the amount of delay, and, in the case of the TE connected at the farthest distance, from 39 N7. Down line, corresponding TE.

A delay means having a one-way delay before returning to the NT via the up line, and an output of the delay means and an output of the variable delay means with a delay amount of O are sent to the NT via the up line of the bus. and a delay difference detection control means for inputting the loop banked training pattern to the down line by the loop bank means, detecting a delay difference, and setting the detected delay difference as the delay amount of the variable delay means, The NT sequentially designates TEs for which delay adjustment is to be performed, and in the designated TE, the training pattern is sent out from the pattern sending means, the delay difference detection control means 15 detects the delay difference, and the detected delay is detected. By using the difference as the delay amount of the variable delay means, the configuration is such that the phases of the channels transmitted from the NT and returned through each TE can be matched.

[Industrial Application Field] The present invention is directed to an NT and a plurality of TEs used in l5DN etc.
The present invention relates to an improvement of a phase synchronization method for a communication system using a multiple access control method in which multiple access control systems are connected via a bus.

The phase synchronization method of the multiple access control system means that the round trip delay (-circular delay) for each TE is adjusted using a variable delay means, and the round trip delay (-circular delay) for each TE is adjusted using a variable delay means. This is to equalize the phases of the channels and enable the NT to read data from each TE using fixed sampling, but it is desirable to be able to set the delay amount of this variable delay means as soon as possible. .

[Conventional technology]

Fig. 3 is a professional three-dimensional diagram of the conventional phase synchronization method, and Fig. 4 is a time chart of each part of Fig. 3.
The case of transmission and reception of TEI-1° which is closest to NTl0° and TEI-n which is farthest from NTl0° is shown.

It is conceivable to periodically provide a training period for determining the amount of delay of the variable delay means, but in order to efficiently provide a training period, the applicant proposed a phase synchronization method that utilizes upstream free areas. It has been submitted as JP-A-61-214636 "Automatic phase control method j" on September 24, 2015.

This overview will be explained with reference to FIGS. 3 and 4.

NTl0' in FIG. 3 includes a free area detection unit 16. Each TE has a training specification section 17 and includes the latest position-1 and the most distant TEL-n,
Random pattern T for phase coincidence detection section 18° delay measurement
A pattern sending circuit 12. It has a variable delay unit 13, and when an empty area detecting unit 16 monitors the uplink and detects an empty area, the training specifying unit 17 sends a training specified area T1 as shown in FIG. 4 (NT) transmission. is set to 1 and transmitted to the TE from the downlink.

For locations-1 and 1-n, the (recent TE) (farthest T) in Figure 4 is
As shown in the reception of E), the training designated area Tl is
When the pattern sending circuit 12 receives the random pattern T, the pattern sending circuit 12 sends out a random pattern T, as shown in FIG. 13 from the up line to NT10°.

NTl0' reads with fixed sampling and the fourth
As shown in the transmission in the figure (NT), the detection pattern is returned.

In this case, the random pattern T transmitted from the farthest TEI-n is NTl0, as shown in the reception in FIG. 4 (NT).
Since the receiver will be picked up at the time slot that the receiver should be picked at ',
Send t as a detection pattern, and find the farthest T E 1-
At n, the detection pattern L is received as shown in the reception of (the farthest TE) in FIG. 4, and the phase matching detection section 18 compares it with T. shall be.

The random pattern T sent out from the recent TEI-1 is
As shown in the reception of (NT) in FIG. 4, in NT10'', reception is not received in the time slot that should be taken, so the returned signal is different from the random pattern T, and the phase matching detection unit 18 of TEI-1 matches it. is not detected, the delay amount of the variable delay section 13 is sequentially increased, and a random pattern is sent out from the pattern sending circuit 12 each time.

Then, the transmitted random pattern T will be received in the time slot that it should be received on the NTl0゛ side, and at this time, in the phase coincidence detection section 18, the random pattern T and the folded end will be equal. , the amount of delay at this time is fixed, and the data transmission state is established.

As described above, the delay amount of the variable delay section 13 is determined, the transmission frame is delayed by the variable delay section 13, and the delay time (Tdi) within the TE is adjusted. The propagation time 2Tpi+'r'ai) becomes constant, and the phase at the receiving end of NT10° is synchronized.

Note that when the training designated area T1 is 0, the TE transmits data.

[Problem to be solved by the invention]

However, in the conventional phase synchronization method described above, in order to determine the delay amount of the variable delay section 13 of the TH, the delay of the variable delay section 13 is delayed until the random pattern T transmitted from the TE and the pattern returned back match. Since the amount is gradually changed and a random pattern is sent each time from the pattern sending circuit 12 to be determined, there is a problem that it takes time.

An object of the present invention is to provide a phase synchronization method that can quickly determine the amount of delay of a variable delay section in a TE.

[Means to solve the problem]

FIG. 1 is a basic diagram of the present invention.

As shown in FIG. 1, NTl0 and multiple TEIs.

In a multiple access control type communication system in which NTs are connected by a bus, the NT 10 is provided with a loopback means 11 for looping back a signal from the up line of the bus to the down line of the bus.

Further, each TEL, . In the case of a TEn, the delay means 14 has a round-trip delay amount from 3iNT10 through the down line, the TE, and the up line to return to the NT 10, and the output of the delay means 14 and the delay amount are O. The output of the variable delay means 13 is sent to the NTl0 via the up line of the bus, the loopback means 11 inputs the looped back training pattern to the down line, detects the delay difference, and detects the detected delay difference. A delay difference detection control means 15 is provided which uses the delay difference as the delay amount of the variable delay means 13.

Then, the NT10 sequentially designates TEs for which delay adjustment is to be performed, and in the designated TEs, the training pattern is sent out from the pattern sending means 12, and the delay difference detection control means 1
In step 5, by detecting the delay difference and using the detected delay difference as the delay amount of the variable delay means 13, it is possible to match the phases of the channels transmitted from the NT10 and returned through each TE. Make it possible.

[Function] According to the present invention, the NT10 sequentially designates the TEs for which delay adjustment is to be performed, and the designated TEs transmit the training pattern from the pattern sending means 12 in the case of the TEn connected to the farthest distance. The signal is inputted to the delay difference detection control means 15 via the delay means 14 having a round trip delay amount.

Further, the training pattern from the pattern sending means 2 is transmitted to the NT1. The signal is then looped back to the down line by the loopback means 11 and input to the delay difference detection control means I5 of the TEL.

The delay difference detection control means 15 detects a delay difference from both inputs, and uses the detected delay difference as the delay amount of the variable delay means 13.

That is, the amount of delay of the variable delay means 13 can be determined by sending out the training pattern of - degrees.

Then, the one-round delay amount of each TE becomes equal.

Therefore, it is possible to match the phases of the channels transmitted from NT10 and returned through each TE, so NT
l0 can be read with fixed sampling.

〔Example〕

FIG. 2 is a block diagram of a phase synchronization method according to an embodiment of the present invention.

In FIG. 2, NTl0 is provided with a loopback circuit 11, and each TEI...n is provided with a pattern sending circuit 12 that sends out a random pattern as a training pattern, and in the case of TEn connected the farthest distance. A delay circuit 14, a variable delay section 13, and a register 1 having a round-trip delay amount of
5-1.15-2, and a delay difference detection circuit 15-3 for detecting a delay amount, which is a phase difference between the random patterns stored in the register 15-1.15-2, and an up/down counter 15-4.

Therefore, NTl0 sequentially designates TEs for which delay adjustment is to be performed.

The designated TE transmits a random pattern from the pattern sending circuit 12 via the delay circuit 14 and the variable delay unit 13, which is initially set to a delay amount of O.

Then, the random pattern that has passed through the variable delay section 13 is
The loopback circuit 11 of NTl0 passes through the upstream line of the bus.
is looped back and passed through the down line to register 15-1.
is entered and stored.

On the other hand, the random pattern passed through the delay circuit 14 is input to and stored in the register 15-2.

Therefore, the delay difference detection circuit 15-3 determines how much the random pattern passing through the delay circuit 14 and stored in the register 15-2 is delayed from the random pattern passing through the variable delay unit 13 and stored in the register 15-1. A difference in delay amount is detected and the delay difference is input to an up/down counter 15-4.

Since the delay difference is a delayed delay difference, the up/down counter 15-4 counts up by the value of the delay difference, holds this value, and outputs it to the variable delay section 13. The variable delay unit 13 delays and fixes the up-count value.

Data transmission is then performed through the variable delay section 13.

That is, the amount of delay of the variable delay section 13 can be determined by sending out a random pattern once.

The above explanation was made by using a random pattern as the training pattern, but this would send out a pattern with a change point like 000111 and register 15-1.15.
The delay difference at the change point at -2 may be detected by the delay difference detection circuit 15-3.

Further, if the terminal device is connected to the bus via a terminal adapter, the delay amount of the variable delay section may be determined by the terminal adapter.

[Effects of the Invention] As described in detail above, according to the present invention, the delay amount of the variable delay section 13 in each TE can be quickly determined.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of a phase synchronization system according to an embodiment of the present invention, Fig. 3 is a block diagram of a conventional phase synchronization system, and Fig. 4 is a block diagram of a phase synchronization system according to an embodiment of the present invention. 4 is a time chart of each part in FIG. 3. In the figure, 1 and n are terminal devices, 1010'' is a network termination device, 11 is a loop bank means, a loop back circuit is a pattern sending means, a pattern sending circuit is a variable delay means, a variable delay unit is a delay means, Delay circuit, is delay difference detection control means, -1, 15-2 are registers, -3 is delay difference detection circuit, -4 is up/down counter, is free area detection section, is training designation section, is phase-defeat detection Show part.

Claims (1)

[Claims] In a communication system using a multiple access control method in which a network termination device (10) and a plurality of terminal devices (1, . . . n) are connected via a bus, the network termination device (10) includes a bus. loopback means (11) for looping back signals from the upstream line of the bus to the downstream line of the bus;
), and each terminal device (1, . . . n) is provided with a pattern sending means (12) for sending out a training pattern, and a variable device that inputs the output of the pattern sending means (12) and can change the amount of delay. In the case of the delay means (13) and the terminal device (n) connected at the farthest distance, return to the network terminating device (10) via the down line, the terminal device, and the up line from the network terminating device (10). The training pattern of the output of the delay means (14) and the output of the variable delay means (13) with the delay amount of 0 are transmitted via the upstream line of the bus. Sending the training pattern to the network terminal device (10) and inputting the training pattern looped back to the downlink by the loopback means (11), detecting the delay difference,
Delay difference detection control means (15) is provided which uses the detected delay difference as the delay amount of the variable delay means (13), and the network termination device (10) sequentially designates the terminal devices to which delay adjustment is to be performed, and In the terminal device, the training pattern is sent out from the pattern sending means (12), a delay difference is detected by the delay difference detection control means (15), and the detected delay difference is transmitted to the variable delay means (13). A phase synchronization method characterized in that by setting a delay amount of