JPH03134774A - Logic simulation method - Google Patents

Abstract

PURPOSE:To secure the delay precision and to perform simultation at the high speed by executing the simulation with a precision according with each description level of logical operation description, logic level description, and gate/ transistor level description. CONSTITUTION:An arbitrary delay time based on a input signal change time is set to the output signal in the case of a logical operation level model, and a defined delay time of all busses between the input signal and the output signal is set to the output signal in the case of a function logic level mode, and an arbitrary delay time is set to the output signal in the case of a gate/ transistor level model. For example, logical operation level model description is compiled like an object 213 for logical operation, and function logic level model description is compiled like an object 214 for function logic. Thus, the delay precision according with the description level is secured and the processing is executed at a high speed in accordance with the description level.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses three models as logic simulation models for a target logic circuit: a logic operation level model, a functional logic level model, and a Goo1~/transistor level model. Concerning logical simulation methods that can be mixed.

[Conventional technology]

Conventionally, in the logic verification of an ASIC such as the one shown in Figure 3, which includes a mixture of gate/transistor level description, I-function logic level description, and logic operation level description, it has been possible to find a CPU with no logic defects.
In order to expand gates to the core and guarantee unnecessary delay accuracy, low-speed gate-level logic simulations were performed.

Also, “Nikkei Electronics 1980.12.8 issue ρ
As handled in ρ172 to 204, the above three models cannot be mixed in the logic between each register, and the delay related to the logic between the registers is usually inserted at the final stage. It was only. Therefore, it cannot be said that the delay accuracy corresponding to the description level is guaranteed, and the method is flawed as a three-model mixed logic simulation method for circuits such as ASICs where delay errors occur frequently.

[Problem to be solved by the invention]

In the above conventional technology, the gate expansion method guarantees unnecessary delay accuracy, resulting in only slow processing performance. On the other hand, the method of uniformly inserting a delay at the final stage for register-register logic has a delay accuracy that is not guaranteed according to the description level. Delay accuracy is not guaranteed.

An object of the present invention is to guarantee delay accuracy according to the description level and to achieve high-speed processing performance according to the description level.

[Means for Solving the Problems] In order to achieve the above objective, the logic behavior level model has an input signal that is determined from the state of the model and the input signal to the model. It is now possible to set an arbitrary delay time for the output based on the signal change time.

Furthermore, regarding the functional logic level model, it has become possible to set a defined delay time in the output signal for every path from the input signal to this model to the output signal to this model. Finally, regarding the gate/transistor level model, as in the past, we have made it possible to set an arbitrary delay time for the output signal with 6 or more, making it possible to execute simulations that can guarantee delay accuracy according to each description level.

[Effect]

Logical behavior level model description is logical behavior object 2
13 (Figure 10). The event registration function PUTSIG in the object allows desired delay time management. Further, the functional logic level model description is compiled as a functional logic object 214 (FIG. 10). The delay time can be set by knowing the path between the event-propagated input signal and the changing output signal.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a flow diagram of a logic simulation system as an embodiment of the present invention. Figure 6.

This will be explained with reference to FIG.

As shown in FIGS. 6 and 8, logical operation level description 81
3 (201), functional logic behavior level description 613 (2
02), gate/transistor level description 611, 61
Regarding the target circuit in which 2,614 (203) are mixed,
Source files 205, 2 corresponding to each level
06,207 is created. On the other hand, a logical file 208 is created from the structural description 204 regarding the connection relationship between each description.

Next, compile each source file209゜210
．． 211, the logical operation object 21
39 function logic object 214° gate/transistor object 215 is created. On the other hand, a structure table 216 is created by logically compiling 212 the logical file.

Next, the above calculation objects 213, 214° 215
While appropriately calling 217, a logic simulation is executed on the structure table 216 in a time map event-driven manner, and a simulation result 218 is output.

FIG. 4, FIG. 6, and FIG. 8 show an example of the present invention.
FIG. 2 is an explanatory diagram of a logical description model.

611, 612, 614, 811, 812° 814 are gate/transistor level description models. 613.
41 is a functional logic level description model, which is an example of a pool type. 813 is a logical behavior level description model, and C
written in language. d in Figures 4, 6, and 8
+(i=1°3.4), the delay times 613 and 813 are functionally completely equivalent.

By the way, the logics of 41, 61, and 81 are also functionally equivalent. In order to speed up the simulation, it is considered effective to run the simulation with a delay of 0, as shown in Figure 41, but the possibility of missimulation in this case is explained using Figures 5 and 7. do. FIG. 5 corresponds to FIG. FIG. 7 is a time chart for FIG. 6. ■All of 1 to 4 are 0
;When Is and Is are 1, when ■7 changes from 0 to 1 at the rise of φl, the final output ○ always changes from O to 1 at φ2 in the same cycle because there is a delay O in Figures 4 and 5. However, in reality it is Figure 6.

As shown in FIG. 7, if there is a good delay d3, the final output ○ may change from 0 to 1 in the next cycle φ2. In this way, accurate simulation can only be performed by guaranteeing delay accuracy according to each level in the mechanism logic level description and the logic operation level description (although no example was shown here).

FIG. 1 shows a logic simulation execution control flow as an embodiment of the present invention. Logical simulation is event extraction 12. Event propagation 13, calculation execution 15, 1
7, 19 and event registration 21 are repeatedly executed until the timer 11 reaches the simulation end time 22. Figures 9 to 1 center around the delay time setting units 16, 18, and 20 to ensure delay accuracy according to each level.
The simulation execution control method shown in FIG. 1 will be explained using FIG. 2.

FIG. 11 and FIG. 12 show an outline of a simulation execution control table as an embodiment of the present invention. The structure table 111 includes an element table 112, a fine table 113. It consists of a fan-out table 114.

One element table 112 is created corresponding to the description model.

The calculation execution object start address indicates the start address at which each calculation object 213, 214, 215 in FIG. 2 is loaded onto the computer.

The other element table 112 includes a fine table 113. which has fan-in fan-out information for connection between elements and the output signal value of the element. fan out table 11
4 stores the start address of the fine destination fan-out destination element of each element.

A time loop 121 in FIG. 12 is a simulation time management table that manages events at each time.

The event 122 consists of the start address of the element whose signal has changed and the output signal value after the change. The activated element table 123 is an area for storing the start address of the element table to be calculated.

9 and 10 show simulation flows of the functional logic level description model 613 of FIG. 6 and the logical behavior level description model 813 of FIG. 8, using the time chart FIG. 7 as an example.

Figure 9 shows event extraction 12. Event propagation 13 is shown. The signal change from 0 to 1 occurring in the input signal 7, that is, the event 122 occurs at time t on the time loop 121:
It is registered in to. Take this event and
Rewrite the output signal value from O to 1 for the element table 112 of I7, learn the fan-out destination Q3 of F from the fan-out table, and activate Q3 in the element table 123.
Register.

FIG. 10 shows calculation execution 16, 18, 20 and event registration 21. Take out Q3 from the activation element table,
The first address PQ3 of the operation execution object in the element table 112 of Q3 is known.

Branch and link is performed to 214 in the case of a functional logical level description model, and to 213 in the case of a logical behavioral level description model. At that time, Q3's fine destination Is, Is,
It is necessary to pass the output signal value of I7 to 213.214 as an argument. The function PUTSIG of 213 is the output signal value q
Set the value to and time the event '=to+d
The event to be registered in a is set at time t = t o +
It has a function of notifying the event registration processing unit 21 of registration in d a.

On the other hand, in the functional logic object 214, a value is set to the output signal value q by executing a pooled operation, and a delay is set from the path of the event-propagated input signal (C in this example) and the changed output signal (q). Know the time d3.

In the event registration 21, the above-mentioned occurrence event 122 is registered on the time loop 121.

The simulation execution control described above makes it possible to execute a simulation that guarantees delay accuracy at each level.

〔Effect of the invention〕

According to the present invention, since it is possible to execute simulations with accuracy according to each description level of logical behavior level description, functional logic level description, and gate/transistor level description, AS that uses an already designed CPU core etc.
In IC simulation, delay accuracy is guaranteed and at the same time, high-speed logic simulation can be executed compared to all-gate expansion. Logic operation level description 1 Iso structure When logic level description and gate/transistor level description account for 80%, 15%, and 5% of all gates, respectively, it is possible to simulate approximately 8 times faster than simulation when all gate layers are open. It is.

[Brief explanation of the drawing]

Fig. 1 is a simulation execution control flow diagram of an embodiment of the present invention, Fig. 2 is a logic simulation system flow diagram, Fig. 3 is a block diagram showing an example of ASIC, Figs. 4, 6, and 8. is an explanatory diagram of the logical description model, Figure 5,
7 is a simulation time chart of an embodiment of the present invention, and FIG. 9 is a simulation time chart of the embodiment of the present invention. Figure 10 is a simulation execution control flow diagram, Figure 11
12 are schematic diagrams of the simulation execution control table. ￥、Z 目 3 fig.

Claims (1)

[Claims] 1. In logic verification of a logic circuit consisting of a circuit that has already been designed and has no logic defects and a circuit to be designed, a logic behavior level model, a functional logic level model, and a gate are used as logic simulation models for the two circuits. /Transistor level models can be mixed, and for the logic operation level model, the input signal change time is used as a reference for the output signal of this model, which is determined from the state of this model and the input signal to this model. For functional logic level models, any delay time defined for every path from the input signal to this model to the output signal to this model can be set to the output signal. In the gate/transistor level model, it is possible to perform simulations while ensuring delay accuracy according to each description level, such as setting an arbitrary delay time for the output signal of the gate or transistor. A logical simulation method characterized by being capable of.