JPH03133115A - Multilayer ceramic chip capacitor and manufacture thereof - Google Patents

Abstract

PURPOSE:To assure the long life and the excellent reliability by a method wherein the material of inner electrodes is Ni or an Ni alloy while the area ratio of grain boundary phase in the section of dielectric layers is 2% or less. CONSTITUTION:Inner electrodes 21, 25 and dielectric layers 3 are alternately laminated while the material of the dielectric layers 3 is to be titanium oxide base, titanic acid base compound oxide and zirconic acid base compound oxide or the mixture thereof. The area ratio of grain boundary phase excluding the grain part comprising the dielectric layers 3 in the arbitrary section of the dielectric layers 3 is restricted within the range not to exceed 2% preferably 0.5-1% and most preferably around 0.5-0.7% resulting in the shorter life and the deterioration in the reliability out of such a range. Through these procedures, the long life and excellent reliability can be assured.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a multilayer ceramic chip capacitor, particularly to improvements in dielectric layers.

<Prior Art> A multilayer ceramic chip capacitor is usually manufactured by laminating a paste for internal electrodes and a paste for dielectric layers by a green sheet method, a printing method, etc., and then firing them together for a period of time.

Pd or a Pd alloy is generally used for the internal electrodes, but since Pd is expensive, relatively inexpensive Ni or Ni alloys are being used.

By the way, when the internal electrodes are made of Ni or Ni alloy, the electrodes will be oxidized if fired in the atmosphere.

For this reason, in -M, after the binder is removed, the dielectric layer is fired at an oxygen partial pressure lower than the equilibrium oxygen partial pressure of Ni and NiO, and the dielectric layer is reoxidized by heat treatment.

In this case, SiOz is usually added as a mineralizer in order to densify the dielectric material. Furthermore, β203 and the like are often mixed into the process.

It is thought that these so-called grain boundary phase components including Bad, Ti12, etc. cause a decrease in insulation resistance when firing is performed in a reducing atmosphere.

Furthermore, in order to prevent a decrease in insulation resistance due to reduction of the dielectric layer, addition of Mn, substitution of Ca, etc. are also performed.

<Problems to be Solved by the Invention> However, multilayer chip capacitors with internal electrodes made of Ni or Ni alloys are more difficult to manufacture than multilayer chip capacitors with internal electrodes made of Pd, which are manufactured by firing in the atmosphere.
There are problems with the extremely short lifespan of insulation resistance (and low reliability).

An object of the present invention is to provide a multilayer ceramic chip capacitor having a long life and high reliability by improving the dielectric layer of the multilayer chip capacitor having internal electrodes made of Ni or Ni alloy, and a method for manufacturing the same. It is in.

Means for Solving the Problems> Such objects are achieved by the following inventions (1) to (8).

(1) A multilayer ceramic chip capacitor having an internal electrode and a dielectric layer composed of grains and a grain boundary phase, wherein the material of the internal electrode is Ni or a Ni alloy, and a cross section of the dielectric layer A multilayer ceramic chip capacitor characterized in that the area ratio of a grain boundary phase is 2% or less.

(2) The multilayer ceramic chip capacitor according to (1) above, wherein the grain boundary phase is an oxide phase containing A e 20 s and SiOx.

(3) The above (2) wherein the content of Al2O3 is 15% by weight or more and the content of 5iOa is 15% by weight or more.
The multilayer ceramic chip capacitor described in .

(4) The multilayer ceramic chip capacitor according to any one of (1) to 3) above, wherein the dielectric layer contains a dielectric oxide of the following formula.

Formula [(Bat-x-y CaxSry)O1m・(Ti
zZrjoz (in the above formula, 0.05≦x≦0.25. 0≦y≦0.05.0.05≦Z≦0, 20.1.00
0≦m≦1.020. )(5) The multilayer ceramic chip capacitor according to any one of (1) to 4) above, wherein an oxide layer having a composition different from that of the dielectric layer is formed around the internal electrode.

(6) The multilayer ceramic chip capacitor according to (5) above, wherein the oxide layer contains one or more selected from oxides of Mn, P, and Fe.

(7) The multilayer ceramic chip capacitor according to (5) above, wherein the oxide layer has a layer containing a P oxide and a layer containing a Mn oxide.

(8) A dielectric material and an internal electrode material of Ni or Ni alloy are laminated and fired at an oxygen partial pressure of 3 x 10"9 atm or less, at a temperature of 900 to 1200°C and an oxygen partial pressure of 10" atm.
A method for manufacturing a multilayer ceramic chip capacitor, characterized in that the chip capacitor according to any one of (1) to 7) above is manufactured by performing heat treatment at a temperature of m or more to reoxidize the dielectric layer.

Effect> The dielectric layer of a multilayer ceramic chip capacitor is composed of grains and grain boundary phases.

This grain boundary phase usually contains oxides of materials constituting dielectric materials or internal electrode materials, oxides of materials added separately, and oxides of materials mixed as impurities during the process. It is made of glass or vitreous material.

The inventors of the present invention have continued to research whether this grain boundary phase has some relationship with the life of the capacitor, and have found that the smaller the grain boundary phase, the longer the life of the capacitor.

Although the interrelationship between the grain boundary phase and lifetime has not been completely elucidated, the grain boundary phase in the dielectric layer serves as a passageway for various ions during migration, and when this grain boundary phase decreases, migration occurs under load. It is thought that it will be suppressed.

In the manufacturing method of the present invention, after the binder removal treatment, firing and heat treatment can be performed under predetermined conditions to reduce the grain boundary phase.

The multilayer ceramic chip capacitor of the present invention, in which the grain boundary phase in the dielectric layer is reduced in this way, has a lifespan approximately 2 to 3 times longer than conventional capacitors, and excellent reliability. can get.

<Specific structure of the invention> Hereinafter, the specific configuration of the present invention will be explained in detail.

1 and 2 show preferred examples of the multilayer ceramic chip capacitor of the present invention, respectively.

The multilayer chip capacitor 1 includes internal electrodes 21.25,
Dielectric layers 3 are alternately laminated, and each internal electrode 21.25
It has a pair of external electrodes 51 and 55 that are connected to.

In the present invention, the internal electrode 21.25 is formed of Ni or a Ni alloy, and in this case, the Ni alloy includes Ni containing 95% by weight or more of Ni, and M n %Cr s
It is preferable that it is an alloy with one or more of AI2, co, etc.

According to the present invention, these can have sufficient life and reliability.

Note that Ni or Ni alloy contains 0 as a trace component.
．． P or the like may be contained in an amount of 1% by weight or less.

Conditions such as the thickness of the internal electrodes 21.25 may be determined as appropriate depending on the purpose and use, but the thickness is usually about 1 to 5 microns, particularly about 2 to 3 microns.

Various dielectric materials may be used as the material for the dielectric layer 3, but titanium oxide, titanate complex oxide, zirconate complex oxide, or a mixture thereof is preferable. As titanium oxide type, NiONlo is available as needed.
lCuOl 04 , Al2zOs , MgO1Si
Examples of titanate-based composite oxides such as T i Oa containing n□ include B a T i Os, S r T i O3
, CaTiOa, MgTiO3, and mixtures thereof.

Among these, titanate-based composite oxides, particularly dielectric oxides of the following formula, are preferred in the present invention.

Formula [(Ba+-x-y CaxSry)Olm・(T1
+-*Zrt)Ox In this case, X is 0.05 to 0.25
, especially 0.06 to 0.10, y is O to 0.05, especially 0
~0.01. z is 0.05 to 0.20, especially 0.15 to
0.20%m is 1.000 to 1.020, especially 1.00
It is preferable that it is 2-1.015.

Then, further add SiO□ from 0.05 to It is preferable to contain about 0.25% by weight.

Further, Mn oxide, AI2 oxide, Ni oxide, Mg oxide, Co oxide, Hf oxide, etc. may be contained in an amount of about 0.5% by weight or less.

Conditions such as the number of laminated layers and the thickness of the dielectric H3 may be determined as appropriate depending on the purpose and application.

Usually the number of laminated layers is about 1 to 1001, especially about 5 to 50,
The thickness is about 5 to 50 microns, especially about 10 to 20 microns.

Further, the average particle diameter of the grains of the dielectric layer 3 is 1 to 5 μm.
It is preferable that the degree of

In the present invention, the area ratio of the grain boundary phase, which is a portion other than grains constituting the dielectric layer 3, is 2% or less, preferably 0.5 to 1%, in any cross section of the dielectric layer 3. , particularly preferably about 0.5 to 0.7%.

If it exceeds the above range, the life span will be shortened and reliability will tend to decrease.

Also, if the size is too small (it is difficult to form the dielectric layer 3),
The densification of the dielectric tends to be insufficient.

Note that the area ratio of the grain boundary phase can be measured by taking a photograph using a scanning electron microscope and calculating it from the photograph.

This grain boundary phase usually consists of oxides of materials that constitute the dielectric material or internal electrode materials, oxides of materials added separately, and oxides of materials mixed as impurities during the process. Usually made of glass or vitreous material.

In the present invention, the grain boundary phase is 15% by weight of SiO.
Above, more preferably about 25 to 50% by weight, Aβ, O
s at 15% by weight or more, more preferably 20 to 50% by weight
Preferably, the oxide phase contains a certain amount of oxide phase.

In such a case, the life-improving effect of the present invention is further improved.

1. In addition, the grain boundary phase contains, for example, Ca, Fe, and Mn within a range of 55% by weight or less.

Zr, P, Ti%Ba, Ni, Sr, etc. may be contained in the form of some oxide.

In this case, SiOz, Ba, Ca, Sr.

Ti, Zr, etc. are mainly supplied from the composition of the dielectric material, and Al2Os is mainly mixed as an impurity during the process, and F
e, P, etc. are mainly supplied from impurities of the internal electrode material and dielectric material, and P, Mn, etc. are mainly supplied from the Mn compound and P compound added to the dielectric material and form the grain boundary phase. Form.

Further, in the present invention, as shown in FIG.
It is preferable that an oxide layer 4 having a composition different from that of the dielectric N3 is formed around 1.25.

The material of the oxide layer 4 may contain at least one type of various oxides (in that case, an even more excellent life-improving effect can be obtained).

In this case, if the oxide layer 4 contains one or more selected from Mn oxide, P oxide, Fe oxide, etc., the life will be further extended and excellent reliability will be obtained. It will be done.

Moreover, which of the following is a titanic acid-based composite oxide, especially in the case of the above formula, -M (I) gives a life-enhancing effect.

Among these, in the present invention, particularly high effects are observed when Mn oxide is included.

In the case of Mn oxide, its content is 1 to 99 in terms of MnO.
It is preferably about 10 to 60% by weight, particularly preferably about 30 to 45% by weight.

In addition, when containing Mn oxide, in addition, for example, Al
1.Si, Ca, Ni, Fe%Ba.

Ti, Zr, P, etc. are usually contained in the form of oxides.

The Mn oxide is usually contained in the oxide layer mainly from a Mn compound added to the dielectric material as described below.

In addition, SL, Ca%Ba%Ti, Zr, P, etc. are mainly supplied from the composition of the dielectric material, Ni is supplied from the internal electrode material, and furthermore, Fe, P, Al1, etc. are mainly supplied from the internal electrode material. It is supplied from impurities of the electrode material and dielectric material and is contained in the oxide layer.

In the case of P oxide, its content is P2O, converted to 011~
It is preferably about 99% by weight, more preferably 3 to 30% by weight, particularly preferably about 15 to 25% by weight.

In addition, when containing P oxide, in addition, for example, Ti5
Ba, Fe, Al2, Si, Ca.

Zr, Mn, etc. are usually contained in the form of oxides.

P oxide is usually contained as an impurity in the dielectric material or contained in the oxide layer from an added P compound. It is usually contained in the form of phosphate.

Furthermore, Ti, Ba, Ca, Zr, SL, etc. are mainly supplied from the composition of the dielectric material, Mn is supplied from the Mn compound added to the dielectric material, and furthermore, Fe, Aρ, etc. are mainly supplied from the composition of the dielectric material. It is supplied from impurities of the internal electrode material and dielectric material and is contained in the oxide layer.

These oxides of Mn and P, when deposited in the oxide layer, function as a barrier layer to prevent migration of Ni ions during loading.

In the case of Fe oxide, the content thereof is preferably about 0.1 to 99% by weight, more preferably about 0.5 to 30% by weight, particularly preferably about 5 to 20% by weight in terms of Fe z Os.

In addition, when containing Fe oxide, in addition, for example, Al
1. Si, Ca, Ti%Ni%Ba.

Zr, Mn, P, etc. are usually contained in the form of oxides.

Fe oxide is mainly supplied from impurities of the internal electrode material and the dielectric material, and is contained in the oxide layer.

Furthermore, Si, Ca, Ti%Ba%Zr, Mn, etc. are mainly supplied from the composition of the dielectric material, Ni is supplied from the internal electrode material, and Al1, P, etc. are mainly supplied from the internal electrode material. It is supplied from impurities of the dielectric material and contained in the oxide layer.

By the way, the grains constituting the dielectric layer 3 contain Fe components contained in the raw material itself or F contained during the process.
Contains the e component, which causes a shortened lifespan.

Therefore, in the case of Fe oxide, unlike the above-mentioned Mn oxide and P oxide, it is considered that it collects in oxide M4, reduces the Fe component in the grain, and improves the life.

The thickness of such an oxide layer 4 is 0.01 to 1μ, especially 0.
．． It is preferable that the time is about 0.05 to 2 μs.

Below the above range, the effects of the present invention tend to decrease;
If it exceeds the above range, the power storage capacity, which is the original function of a capacitor, will be reduced. In other words, not only the condition value is lowered, but also the breakdown voltage is lowered, the life span is shortened, and the reliability is also lowered.

Further, the oxide layer 4 may have a one-layer structure, but if it has a two-layer structure as shown in the figure, the life of the present invention is further improved.

In the case of a two-layer structure, one layer contains P oxide and the other layer contains M.
Particularly preferred is one containing n-oxide at a high concentration. Further, it will be even more effective if Fe oxide is further included.

In this case, P oxide is included in the lower oxide layer 41, and Mn
The oxide is contained in the upper oxide layer 45. Therefore, the lower oxide layer 41 becomes a base layer and the oxide N45 can be formed more easily than in the case of IH. Specifically, the oxide layer 4
5 can be formed, and in addition, the content of Mn oxide can be increased.

Note that although Fe oxide is normally contained in the upper oxide layer 4S, it may be contained in the lower oxide layer 41.

The content of Mn oxide in the upper oxide layer 45 is preferably about 1 to 99% by weight, preferably about 10 to 50% by weight, particularly preferably about 25 to 40% by weight in terms of MnO.

Further, the content of Fe oxide in the upper oxide layer 45 is Fe
0.1 to 99% by weight in terms of 2rs, preferably 0.1 to 99% by weight
It is preferably about 25% by weight, particularly preferably about 5 to 15% by weight.

Furthermore, Tf, Ni, Ca, Ba, Zr, Ag, S
i, P, etc. may be contained in the form of an oxide.

Further, the content of P oxide in the lower oxide layer 41 is P x
0.1 to 99% by weight in terms of OS, preferably 3 to 30%
It is preferably about 15 to 25% by weight, particularly preferably about 15 to 25% by weight.

Furthermore, Ba%Ca, Ti, and Zr.

Ag, SL, Mn, Ni, etc. may be contained in the form of oxides.

In this case, the thickness of the upper oxide layer 45 is preferably about 0.005 to 0.995 mm, particularly about 0.05 to 0.2 mm.

Further, the thickness of the lower oxide layer 41 is 0.005 to 0.99
It is preferably about 5μ, particularly about 0.05 to 0.2 scales.

In addition, the oxide layer 4 may have a structure of three or more layers.

The external electrodes 51.55 are usually made of Cu, Cu alloy, Nf, Ni alloy, or the like.

Note that, of course, Ag, Ag-Pd alloy, etc. can also be used.

The thickness of the external electrodes 51,55 is arbitrary and may be determined as appropriate depending on the purpose and use, but is usually about 10 to 50.

The shape and size of such a multilayer chip capacitor 1 may be determined as appropriate depending on the purpose and use. For example, in the case of a rectangular parallelepiped, it is usually 1.6 to 3.2 mm x 0.
It is approximately 8 to 1.6 mm x 036 to 1.2 mm.

Next, a method for manufacturing a multilayer ceramic chip capacitor according to the present invention will be explained.

First, a paste for the dielectric layer 3, a paste for the internal electrodes 21.25, and a paste for the external electrodes 51.55 are manufactured, respectively.

As the raw material powder for the dielectric used when manufacturing the paste for the dielectric layer 3, oxides constituting titanium oxide and titanate complex oxides may be used, and the corresponding oxide dielectric may be used. Depending on the composition of Ti, Ba, Sr, C
Oxides such as a, Zr, etc. may be used.

Furthermore, compounds that become oxides upon firing, such as carbonates, sulfates, nitrates, oxalates, organometallic compounds, etc., may also be used.

These raw material powders usually have an average particle size of about 0.1 to 5 particles.

In addition, as a sintering aid or mineralizing agent, S i O, l is 0.
．． It is preferable that the content is about 0.05 to 0.25% by weight.

More preferably, those further containing a Mn compound or a P compound, particularly those containing a Mn compound and a P compound.

The content of the Mn compound is preferably about 0.005 to 2% by weight, particularly about 0.05 to 0.5% by weight in terms of MnO.

In this case, any Mn compound can be used.

Examples include oxides such as MnO, carbonates, oxalates, hydroxides, nitrates, sulfates, organometallic compounds, etc.
One or more of these may be used in combination.

In addition, the content of P compound is 0.005 in terms of p, o.
It is preferably about 5% by weight, particularly about 0.01 to 0.05% by weight.

Any compound can be used as the P compound.
Examples include oxides such as P and 05, phosphoric acid, and organic compounds containing P, and one or more of these may be used in combination.

To obtain a dielectric material from such raw material powder, for example, the following procedure may be used.

First, starting materials are blended in a predetermined ratio and wet-mixed using, for example, a ball mill.

Next, it is dried using a spray dryer or the like, and then calcined.

Temporary baking is usually carried out in the air at 800 to 1300°C for about 2 to 10 hours.

Then, it is pulverized using a jet mill, a ball mill, etc. until it reaches a predetermined particle size.

Note that the above-mentioned Mn compound and P compound may be added before or after calcination.

Various additives such as binders, plasticizers, dispersants, and solvents may be used in preparing the paste for the dielectric layer 3. Additionally, glass frit may be added.

Examples of binders include ethyl cellulose, abietic acid resin, polyvinyl butyral, etc. Plasticizers include abietic acid derivatives, diethyl oxalate, polyethylene glycol, polyalkylene glycol, phthalate, dibutyl phthalate, etc. Dispersants include For example, glycerin, octadecylamine, trichloroacetic acid, oleic acid, octadiene, ethyl oleate, glycerin monooleate, glycerin trioleate, glycerin tristearate, mensaden oil, etc. Examples of the solvent include terpineol, butylcarpitol, Examples include toluene and methyl ethyl ketone.

When preparing this paste, the proportion of the dielectric material to the whole is about 50 to 80% by weight, and the binder is about 2% by weight.
-5% by weight, plasticizer 0.1-5% by weight, dispersant 0.
The content of the solvent is about 1 to 5% by weight, and the content of the solvent is about 20 to 50% by weight.

Then, these are mixed and kneaded using, for example, three rolls to form a paste (slurry).

As the conductive material used in manufacturing the paste for the internal electrodes 21.25, Ni, Ni alloy, or a mixture thereof is used.

The shape of such a conductive material is not particularly limited, such as spherical or scale-like, and may be a mixture of these shapes.

In addition, the average particle diameter is 0.1 to 10 μs, and even 0.1
~1- or so may be used.

The organic vehicle contains a binder and a solvent.

As the binder, any known binder such as ethyl cellulose, acrylic resin, butyral resin, etc. can be used.

The binder content is above 1-5% by weight.

As the solvent, any known solvent can be used, such as terpineol, butylcarpitol, kerosene, and the like.

The solvent content is approximately 20 to 55% by weight.

In addition, within a total amount of about 10% by weight or less, if necessary, fractionating agents such as sorbitan fatty acid ester and glycerin fatty acid ester, plasticizers such as dioctyl phthalate, dibutyl phthalate, butyl butyl phthalyl glycolate, and anti-delami For the purpose of suppressing sintering, etc., various ceramic powders such as dielectrics and insulators can be added.

It is also effective to add an organic metal resinate.

As the paste for the external electrodes 51, 55, a normal paste containing the above-mentioned conductive material powder may be used.

The thus obtained paste for the internal electrodes 21 and 25 and the paste for the dielectric 3 are alternately laminated by a printing method, a transfer method, a green sheet method, or the like.

Next, after cutting the laminate into a predetermined size, binder removal treatment and firing are performed. Then, heat treatment is performed to reoxidize the dielectric layer 3.

The binder removal treatment may be performed under normal conditions, but it is particularly preferable to perform it under the following conditions.

Temperature increase rate = 10-300°C/hour, especially 50-b Holding temperature: 600-1200°C, especially 700-900°C Holding time: 045-5 hours, especially 1-3 hours Oxygen partial pressure: 10° 4-10- 9 atm, especially 10-@~
It is preferable to use humidified N2 gas or the like as the 10-9 atm atmosphere gas.

The calcination is carried out at an oxygen partial pressure of 3 x 100 -9 atm or less, preferably 3 x 10 g' to 10' atm, particularly preferably 101 to 10' atm.

If it exceeds the above range, the internal electrodes 21.25 tend to oxidize, and if it is too small, the electrode material tends to abnormally sinter and break off.

The other firing conditions are preferably as follows.

Temperature rising rate: 50-500°C/hour, especially 200-300°C/hour Holding temperature: 1250-1400°C, especially 1300-1380°C Holding time: 0.5-8 hours, especially 1-5 hours Cooling rate: 50-300°C It is preferable to use a humidified mixed gas of N2 and H2 as the atmospheric gas at 500°C/hour, especially at 200 to 300°C/hour.

Heat treatment is performed at a holding temperature or maximum temperature of 900 to 1200
°C, preferably 900-1100 °C, particularly preferably 1
()00 to 1100°C.

Below the above range, the dielectric material is insufficiently oxidized and its life tends to be shortened; when above the above range, the Ni in the internal electrodes not only oxidizes and the capacity decreases, but also reacts with the dielectric base. This tends to lead to shorter lifespans.

Further, the oxygen partial pressure is 10-9 atm or more, preferably 1
0-4 to 10-9 atm, particularly preferably 10-' to
10-9 atm.

If it is less than the above range, it will be difficult to reoxidize the dielectric layer 3 and oxide layer 4, and if it exceeds the above range, the internal electrodes 21, 25 will tend to be oxidized.

The other heat treatment conditions are preferably as follows.

Holding time: 20 to 6 hours, especially 2 to 5 hours Cooling rate: 50 to 5 degrees Celsius/hour, especially 100 to b. It is preferable to use humidified N2 gas or the like as the atmospheric gas.

Note that in order to humidify N2 gas, mixed gas, etc., a wetter or the like may be used, for example. In this case, the water temperature is 5~
The temperature is preferably about 75°C.

Furthermore, the binder removal treatment, firing, and heat treatment may be performed successively or independently.

In addition, when performing the firing independently, the temperature is raised in an N2 gas atmosphere until the holding temperature for the binder removal treatment is reached, and after cooling to the holding temperature or the maximum temperature for the heat treatment, the firing is performed under an N2 gas atmosphere. Cooling.

Further, when heat treatment is performed, the temperature is increased from the holding temperature to the maximum temperature in an N2 gas atmosphere.

The end face of the thus obtained sintered body is polished by, for example, barrel polishing, sandblasting, etc., and an external electrode paste is baked to form external electrodes 51 and 55.

Then, if necessary, a pad layer is formed by plating or the like on the external mold 151.55.

<Example> Hereinafter, the present invention will be described in further detail by referring to specific examples of the present invention.

Example 1 Starting materials BaCO5: 65.28% by weight TiO□: 23.72% by weight Zr0i: 7.49% by weight CaCO5: 2.88% by weight 5ift: 0.18% by weight MnCO5: 0.20% by weight Above The starting materials were mixed in an alumina ball mill for 16 hours.

Then, after drying with a spray dryer, it was calcined in air at a temperature of 1200° C. for 5 hours.

Then, the mixture was ground in a ball mill for 16 hours to obtain a barium titanate dielectric material having an average particle size of 1.4-.

The composition of the obtained dielectric material is as follows.

[(Bao, eicao, oa)O] r, oa
41Tio, asZro, l? )02:99.62
Weight% 5iOi: 0.18% by weight MnO: 0.20% by weight Using this dielectric material, at the compounding ratio shown below,
The mixture was kneaded using three rolls to form a slurry to obtain a dielectric layer paste.

Dielectric material: 100 parts by weight Terpineol = 28 parts by weight Toluene: 14 parts by weight Dispersant 0.2 parts by weight Lacquer: 36.5 parts by weight Next, at the compounding ratio shown below, the mixture was kneaded using three rolls to form a slurry. This was used as a paste for internal electrodes.

Ni: 10.0 parts by weight Terpineol = 93 parts by weight Dispersant: 1 part by weight Lacquer 26 parts by weight Using these pastes, a multilayer ceramic chip capacitor 1 shown in FIG. 1 was manufactured in the following manner.

First, a paste for dielectric layers and a paste for internal electrodes were alternately laminated by a printing method.

Note that the number of stacked dielectric layers 3 is 15.

After cutting into a predetermined size, binder removal treatment, firing, and heat treatment were successively performed under the following conditions.

11 Heating rate: 50℃/hour Holding temperature: 2800℃ Holding time: 2 hours Atmosphere gas: Humidified N2 gas Oxygen partial pressure: 10"9 atm Heating rate: 200℃/hour Holding temperature: 1340℃ Holding time: 2 hours Cooling rate: 300℃/hour Atmosphere gas: Humidified mixture of N2 and N2 Oxygen partial pressure: 10-"ATM heat" Holding temperature: 1100℃ Holding time: 2 hours Cooling rate : 300°C/hour Atmosphere gas: Humidified N2 gas Oxygen partial pressure: 10-9 atm Each of the atmospheric gases was humidified using a wetter at a water temperature of 10 to 35°C.

After polishing the end face of the obtained sintered body by sandblasting, an In-Ga alloy was applied to form a test electrode.

The sizes of the multilayer ceramic chip capacitor l manufactured in this way are 3.2 mm x 1 and 6 mm x 1.
, 2 mm, and the thickness of the dielectric layer 3 is 20-1, and the thickness of the internal electrode 21.25 is 2.5-.

Further, the average particle diameter of the grains of the dielectric layer 3 is 3.0μ
It is.

Then, a scanning electron microscope photograph of the cross section of the dielectric layer 3 was taken, and the area ratio of the grain boundary phase was measured, and it was found to be 0.7%.
No oxide layer was formed around the internal electrodes 21.25.

Note that FIG. 3 is a scanning electron micrograph showing a cross section of the dielectric layer 3, and it can be confirmed that there are few grain boundary phases.

Furthermore, compositional analysis of the grain boundary phase was performed using a scanning transmission electron microscope (STEM), and the results were as follows.

Si oxide (SiO2 equivalent): 31.8% by weight AI2 oxide A60. (conversion): 26.7 wt% Mn oxide (MnO conversion): 0.2 wt% Fe oxide (Feign conversion)
: 1.0% by weight Ni oxide (calculated as NiO) : 1. O
Weight % P oxide P2O3 equivalent): 0.1 weight % Ba oxide (BaO equivalent): 27.7 weight % Ti oxide (
TiO□ conversion): 11.4% by weight Zr oxide (ZrOa
Conversion): 0.1% by weight Next, this capacitor was subjected to an accelerated life test at a temperature of 200° C. and a voltage of 200 V DC, and the life was 8.3 hours.

Example 2 A multilayer ceramic chip capacitor was manufactured in the same manner as in Example 1 under the following firing and heat treatment conditions.

■ Temperature increase rate = 200℃/hour Holding temperature: 1360℃ Holding time = 2 hours Cooling rate = 300℃/hour Atmosphere gas: Humidified mixture of N and N2 Oxygen partial pressure: 10-"atm natural" L Dust holding temperature: 1100°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere gas: Humidified N2 gas Oxygen partial pressure: 10-9 atm In this case, the thickness of the dielectric layer 3 is 20 mm, and the average grain size The diameter is 3.2 doors, the area ratio of the grain boundary phase is 0.6%,
The thickness of the internal electrodes 21.25 is 2.5 mm.

Further, compositional analysis of the grain boundary phase was performed using STEM, and the results were as follows.

Si oxide (SiO2 equivalent): 31.2% by weight AI2 oxide (Aja03 equivalent): 24.4% by weight Mn oxide MnO
Conversion): 0.5 wt% Fe oxide (Fears conversion): 0.7 wt% Ni oxide (NiO conversion): 1.
4% by weight P (calculated as oxide P2O5): 0.1% by weight Ba
oxide, BaO equivalent): 29.3 wt% Ti oxide TiO□ equivalent): 12.2 wt% 22rln Ca oxide (CaO equivalent): 0.1 wt% Zr oxide (
ZrO* conversion): 0.1% by weight When an accelerated life test was conducted, the life was 9.5 hours.

Example 3 A multilayer ceramic chip capacitor having the oxide layer 4 shown in FIG. 2 was manufactured under the following firing and heat treatment conditions in the same manner as in Example 1.

Base heating rate: 200℃/hour Holding temperature: 1320℃ Holding time: 4 hours Cooling rate: 300℃/hour Atmosphere gas: Humidified mixture of N2 and N2 Oxygen partial pressure: 10-"atm heat" L dish Holding temperature: 1100°C Holding time = 2 hours Cooling rate: 300°C/hour Atmosphere gas: Humidified N2 gas Oxygen partial pressure: 1 O-9 atm In this case, the thickness of the dielectric layer 3 is 20 mm, average particle size The diameter is 3.1-1, the area ratio of the grain boundary phase is 0.7%,
The thickness of the internal electrode 21.25 is 2.5 tiles.

Further, compositional analysis of the grain boundary phase was performed using STEM, and the results were as follows.

Si oxide (SiO□ conversion): 30.9% by weight AI2 oxide (A12os conversion): 25.3% by weight Mn oxide MnO
(conversion): o, e weight% Ni oxide NLO conversion)
: 0.1% by weight Fe oxide (Fetus equivalent): 0.
1% by weight P Oxide (calculated as P20a): 0.4% by weight B
(a oxide BaO equivalent): 30. O weight% Ti oxide TiO□ conversion): 11.9 weight% Ca oxide (CaO
(converted): 0.1% by weight Zr oxide (converted to ZrOi): 0
．． 6% by weight Further, the oxide layer 4 is one layer, and its thickness is 0.08 pm. The layer composition of the oxide layer 4 was analyzed by STMH and found to be as follows.

Mn oxide (MnO equivalent): 38.1% by weight Fe oxide (Fe*Os equivalent): 10.6% by weight Aβ oxide AJ
*Os conversion): 0.1% by weight Zr oxide ZrO* conversion)
: 0.1% by weight P oxide p, o (converted): 1.4% by weight Ni oxide (converted to NiO) : 9.6% by weight St oxide (converted to 5in2): 1.3% by weight Ca oxide ( Ca
O conversion): 0.5 wt% Ti oxide (TiO□ conversion): 34.1 wt% Ba oxide (BaO conversion)
: 4.2% by weight When an accelerated life test was conducted, the life was 14.7 hours.

Example 4 A multilayer ceramic chip capacitor having the oxide layer 4 shown in FIG. 2 was manufactured using the following dielectric material and under the following firing and heat treatment conditions in the same manner as in Example 1.

1[(Bao, 5icao, os)o] l 004
・(Tio, asZro, lt) Oa: 99
．． 52 wt% SiO2: 0.18 wt% MnO: 0.30 wt% Heating rate = 200°C/hour Holding temperature: 1340°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere gas: Humidified N2 and N2 mixed gas Oxygen partial pressure: 10-day ATM Demolding 1 Holding temperature: 1100°C Holding time = 3 hours Cooling rate: 300°C/hour Atmosphere gas: Humidified N2 gas Oxygen partial pressure: 10-9 atm In this case, The thickness of the dielectric layer 3 is 20-1, the average particle diameter of the grains is 2.7-1, the area ratio of the grain boundary phase is 0.6%,
The thickness of the internal electrode 21.25 is 2.5%.

Further, compositional analysis of the grain boundary phase was performed using STEM, and the results were as follows.

Si oxide (SiO□ conversion): 28.4 wt% Aβ oxide (AjaOs conversion): 23.1 wt% Mn oxide (MnO conversion): 1.2 wt% Fe oxide (Fears conversion)
: 0.5% by weight Ni oxide (NiO equivalent) : 0.
6 wt% P (calculated as oxide P2O3): 0.4 wt% Ba
Oxide (BaO equivalent): 30.9 wt% Ti oxide (Tie, equivalent): 13.3 wt% Ca oxide (CaO equivalent): 0.6 wt% Zr oxide (ZrO, equivalent):
1.0% by weight The oxide layer 4 has a two-layer structure of the oxide layer 41 and the oxide N45, and the thickness of the lower oxide layer 41 is 0.09-1 and the thickness of the upper oxide layer 1145 is 0.09-1.0% by weight. It is 06 tiles.

The layer composition was analyzed by STEM and found to be as follows.

5 Mn oxide (MnO equivalent): 33.6% by weight Fe
Oxide (Fe*Os equivalent): 9.8% by weight Ni oxide (
NiO equivalent) Near, 1 wt% P oxide (PIOs equivalent): 0.9 wt% Ba oxide (BaO equivalent): 5
．． 9wt% T1 oxide (Tie, conversion): 36.6wt% Other oxides: 6.1wt% 1 P oxide (Pass conversion): 22.5wt% Ba oxide (BaO conversion) Near 1 .2 wt% Mn oxide (
MnO equivalent): 0.7% by weight Fe oxide (Fei
gn equivalent): 1.1% by weight Ni oxide (NiO equivalent):
1.2% by weight Ti oxide (in terms of TiOz): 2.8% by weight Other oxides: 0.5% by weight When an accelerated life test was conducted, the life was 18.2 hours.

Comparative Example 1 A multilayer ceramic chip capacitor was manufactured in the same manner as in Example 1 under the following firing and heat treatment conditions.

■ Temperature increase rate: 200℃/hour Holding temperature: 1340℃ Holding time = 2 hours Cooling rate: 300℃/hour Atmosphere gas: Humidified mixture of N and N2 Oxygen partial pressure: 10-9 atm Holding temperature: 1100°C Holding time: 2 hours Cooling rate: 300°C/hour Atmosphere gas: Humidified N2 gas Oxygen partial pressure: 10-9 atm In this case, the thickness of the dielectric layer 3 is 20-9, and the average particle size of the grains The area ratio of the 2.9-1 grain boundary phase is 2.8%,
The thickness of the internal electrode 21.25 is 2.5-.

Note that FIG. 4 is a scanning electron micrograph showing a cross section of the dielectric layer 3, and it can be confirmed that there are more grain boundary phases than in FIG. 3.

Further, compositional analysis of the grain boundary phase was performed using STEM, and the results were as follows.

Si oxide (SiO□ conversion): 25.4% by weight Aε oxide (A11as conversion): 12.6% by weight Mn oxide (MnO conversion): J, 4% by weight Fe oxide (Fe, O, conversion): 0.
7% by weight P Oxide P 0. (conversion): 0.3% by weight Ba
35.1% by weight Ti oxide T (in terms of LOm): 14.6% by weight Ca oxide (in terms of CaO) : 4.0% by weight Zr oxide (in terms of ZrOi):
3.2% by weight Ni oxide (calculated as NiO): O', 7% by weight
Note that when observed with a scanning electron microscope, the oxide layer 4 was not formed.

Further, when an accelerated life test was conducted, the life was 1.4 hours.

These results clearly demonstrate the effects of the present invention.

<Effects of the Invention> The multilayer ceramic chip capacitor of the present invention has a long life.

Therefore, excellent reliability can be obtained.

When the oxide layer 4 having a composition different from that of the dielectric #3 is provided around the internal electrodes 21 and 25, the effects of the present invention are further improved.

In particular, the oxide layer 4 contains one or more selected from Mn oxide, P oxide, and Fe oxide, and furthermore, the oxide layer 4 contains a layer containing an Mnif oxide and a P oxide. Those with a two-layer structure including layers have a particularly long life (and -layers) and can provide excellent reliability.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are sectional views each showing an example of the multilayer ceramic chip capacitor of the present invention. FIG. 3 is a photograph substituted for a drawing showing the particle structure, and is a scanning electron micrograph showing the dielectric layer of the multilayer ceramic chip capacitor of the present invention. FIG. 4 is a photograph substituted for a drawing showing the particle structure, and is a scanning electron micrograph showing the dielectric layer of a conventional multilayer ceramic chip capacitor. Explanation of symbols l...Multilayer ceramic chip capacitor 21.25
...Inner electrode 3...Dielectric layer 4...Oxide layer 41...Lower oxide layer 45...Upper oxidation initial layer 51.55...External electrode Applicant TDC-K Co., Ltd. Company agent Patent attorney Ishii Remote patent attorney
Increase 1) Tatsuya F Eng G. E Engineering G. F Engineering G. ■G.

Claims (8)

[Claims] (1) A multilayer ceramic chip capacitor having an internal electrode and a dielectric layer composed of grains and a grain boundary phase, wherein the material of the internal electrode is Ni or a Ni alloy, and a cross section of the dielectric layer A multilayer ceramic chip capacitor characterized in that the area ratio of a grain boundary phase is 2% or less. (2) The multilayer ceramic chip capacitor according to claim 1, wherein the grain boundary phase is an oxide phase containing Al_2O_3 and SiO_3. (3) The multilayer ceramic chip capacitor according to claim 2, wherein the Al_2O_3 content is 15% by weight or more, and the SiO_2 content is 15% by weight or more. (4) The multilayer ceramic chip capacitor according to any one of claims 1 to 3, wherein the dielectric layer contains a dielectric oxide of the following formula. Formula [(Ba_1_−_x_−_y Ca_xSr_y)
O]_m・(Ti_1_-_zZr_z)O_2{In the above formula, 0.05≦x≦0.25, 0≦y≦0.05, 0.05≦z≦0.20, 1.00
0≦m≦1.020. } (5) The multilayer ceramic chip capacitor according to any one of claims 1 to 4, wherein an oxide layer having a composition different from that of the dielectric layer is formed around the internal electrode. (6) The multilayer ceramic chip capacitor according to claim 5, wherein the oxide layer contains one or more selected from oxides of Mn, P, and Fe. (7) The multilayer ceramic chip capacitor according to claim 5, wherein the oxide layer includes a layer containing P oxide and a layer containing Mn oxide. (8) The dielectric material and the internal electrode material of Ni or Ni alloy are laminated and fired at an oxygen partial pressure of 3×10^-^9 atm or less, at a temperature of 900 to 1200°C and an oxygen partial pressure of 10^-
8. A method for manufacturing a multilayer ceramic chip capacitor, characterized in that the chip capacitor according to any one of claims 1 to 7 is manufactured by performing heat treatment at ^8 atm or higher to reoxidize the dielectric layer.