JPH0313121A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a software error caused by an alpha line, etc., without increasing energy consumption and delay time by providing a source follower current control means. CONSTITUTION:A source follower control circuit, which controls a current to flow to a source follower transistor Q4, is composed of a transistor Q5 and resistor RSF. When the potential of an input terminal CIN is a low logical level, the transistor Q5 is set in a low current state and an output terminal C is a high logical level. At such a time, the source current of the transistor Q4 is small and the output impedance of the transistor Q4 is high. Accordingly, in such a state, when the potential of a node N1 is momentarily flowered by a spike noise caused by the alpha line, the output of the transistor Q4 is lowered according to a time constant to be determined by product between the output impedance and load capacity and the potential of the output terminal C is not fluctuated but still the high logical level. Thus, without increasing the energy consumption or delay time, durability to the software error to be caused by the alpha line can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device comprising a source-coupled logic circuit (SCFL) or an emitter-coupled logic circuit (ECL). It is.

[Conventional technology]

FIG. 2 is a circuit diagram of a gate circuit constructed from a conventional source-coupled logic circuit (5CFL).

In FIG. 2, the sources of transistors Ql and Q2 are commonly connected to the drain of transistor Q3. Also, the transistor Q1. The drain of Q2 is each resistor R
! 1. ．． It is commonly connected to the cathode of the level shift diode D1 through R, , and the anode of the diode D1 is the ground terminal. It is connected to the. On the other hand, the source of transistor Q3 is connected to negative power supply terminal V through resistor R1.
connected to cc. This transistor Q3 and resistor R
5 constitutes a constant current circuit.

The gate of transistor Q1 is an input terminal C that inputs a signal.
IN, and the gate of the transistor Q2 is connected to a reference voltage terminal V0F that provides a reference potential. Also,
The gate of transistor Q3 is connected to constant current circuit reference voltage terminal vc3. Transistors Ql, Q2. Q
3 and the resistors RD l *R0 and R5 constitute a differential logic section.

Drain potential N1 of transistor Ql is taken out by source follower transistor Q4.

That is, the gate of the transistor Q4 is connected to the drain of the transistor Q1 at the node N1, and the drain of the transistor Q4 is connected to the ground terminal ■. It is connected to the. The source of the transistor Q4 is connected to the drain of the transistor Q5 via the level shifting diode D2, and the source of the transistor Q5 is connected to the negative power supply terminal VSS via the resistor Rsr. This transistor Q5 and resistor R□ constitute a constant current circuit.

Further, a connection point between the diode D2 and the drain of the transistor Q5 is connected to the output terminal C.

Next, the operation of the circuit shown in FIG. 2 will be explained.

The potential of the signal applied to the input terminal CIN is the reference voltage terminal v11! If the potential of transistor Q is higher than that of F,
1 is turned on and transistor Q2 is turned off. Therefore, the current flows through the resistor R1)l, and the potential of the node N1 becomes the resistor R1)
It decreases by the voltage drop at II. This drop in potential is taken out by transistor Q4, and output terminal C becomes a low logic level.

On the other hand, when the potential applied to the input terminal CIN is lower than the potential of the reference voltage terminal V□, the transistor Q1 is turned off and the transistor Q2 is turned on. Therefore, current flows through the resistor RDffi and almost no current flows through the resistor R, so that the potential of the node N1 increases. The increase in the potential of node N1 is taken out by transistor Q4, and output terminal C becomes a high logic level.

FIG. 3 is a circuit diagram combining the gate circuit of FIG. 2 and the D latch circuit.

In FIG. 3, the D latch circuit 20 has a data input terminal R.
, clock terminal CK, reset terminal R2 output terminal Y
, and an inverted output terminal ■, and a clock terminal CK.
A clock signal is applied to the gate circuit 10 via the output of the gate circuit 10 shown in FIG.

The operation of this D latch circuit 20 will be explained.

Since the reset signal R input to the reset terminal R is not related to the essence of the explanation that follows, it is assumed to be at a low logic level here.

First, when the clock signal input to the clock terminal CK is at a low logic level, the data D input to the data input terminal is output to the output terminal y, and the data D obtained by inverting the data D is output to the inverted output terminal. 7 is output.

Then, when the clock signal input to the clock terminal CK becomes a high logic level, this D latch circuit 20 enters the holding state, and the data D output to the output terminal Y and the inverted data output to the inversion output terminal Y Hundreds are retained. Thereafter, even if the logic level of the data D input manually to the data input terminal changes, the output state remains unchanged and remains unchanged.

[Problem to be solved by the invention]

By the way, in recent years, with the progress of miniaturization of devices, soft errors due to alpha rays generated by packages, etc.
This is a situation that cannot be ignored in I.

In addition, it has been reported that the amount of charge collected in GaAs MESFETs when irradiated with alpha rays is 10 times larger than that of Si (IEEE Electron Device Letters).
e Letters, Vol, HD-7+ p, 3
96+ June 1986)) and GaAs static RAM with a soft error rate of 31.
104 times more than charcoal (reported to be a problem)
Digest of Technical Papers (ISSCCDigest of t
electrical paper J p, 138-139:
Feb,, 19B? )), GaA
Similarly to Si, soft errors caused by α rays are a serious problem in S.

In the circuit of FIG. 2, consider the case where the signal applied to the input terminal CIN is at a low logic level and the potential at the node N1 is at a high potential. At this time, the α rays are transmitted to the transistor Q
When irradiated with 1, electron-hole pairs are generated. and,
When electrons are collected in the drain region, the drain potential, ie, the potential of node N1, drops instantaneously. In order to compensate for this drop in potential, the drain is charged by the ground terminal V■ via the resistor RIll, so at least several hundred ps
(picosecond) spike-like pulses are generated. This spike-like pulse, ie, spike noise, causes malfunctions of various circuits.

For example, in the circuit 2 shown in FIG. 3, the input of the clock terminal CK of the D latch circuit 20 is at a high logic level,
Consider the case where the output of output terminal Y maintains a high logic level.

After that, even if the data D input to the data input terminal changes to a low logic level, the output terminal Y and the inverted output terminal
The output state of will not change.

In this state, when the spike-like pulse is generated in the gate circuit 10, this pulse is transmitted to the clock terminal CK of the D latch circuit 20, and the D latch circuit 20 changes from the data holding state to the data writing state. At this time, the input data D is already at a low logic level, so low logic level data is written into the D latch circuit 20, and the output terminal Y
The output from the inverting output terminal Y becomes a low logic level, and the output from the inverting output terminal Y becomes a high logic level, so that the content of the data held is inverted.

Since the spike noise caused by such alpha rays is almost inversely proportional to the capacitance attached to the drain of a transistor, soft errors will become inevitable as elements become smaller in the future.

In order to deal with soft errors in the circuit shown in FIG.
142619) or increasing the current (Japanese Unexamined Patent Publication No. 143019/1983). In addition, in GaAsRAM, there is a method of adding capacity to the critical drain node to make the soft error rate comparable to that of 5iLSI.
cal papers, p, 138-139: Fe
b, 1987) has been proposed. However, these methods have the problem of increasing delay time or power consumption.

This invention was made to solve the above-mentioned problems, and provides a semiconductor integrated circuit device that can avoid the problem of soft errors caused by alpha rays, etc., without increasing power consumption or delay time. The purpose is to obtain.

[Means to solve the problem]

In the semiconductor integrated circuit device according to the present invention, the sources of at least the first transistor and the second transistor are commonly connected to a constant current source, and a current path is switched by a potential applied to the gate of each of the transistors. In a semiconductor integrated circuit device comprising a source-coupled logic circuit that obtains an inverted output and a non-inverted output by extracting drain potentials of a transistor and a second transistor by a first source follower and a second source follower, respectively,
The source follower current control means controls the source follower current of the first source follower when the first transistor is in the off state, when the first transistor is in the on state. The source follower current is controlled to be smaller than the source follower current in the state.

[Effect]

A case will be described in which the source-coupled logic circuit according to the present invention is composed of normally-mario FETs.

When the gate potential of the first transistor is at a low logic level and the first transistor is in an off state, the drain potential of the first transistor is high and the first
The output of the source follower becomes a high logic level. At this time, the source follower current control means controls the source follower current of the first source follower to become small, and the output impedance of the first source follower becomes high. Therefore, in this state, if the drain potential of the first transistor drops instantaneously due to spike noise caused by alpha rays, the output of the first source follower will be reduced by a large amount of time determined by the product of its output impedance and load capacitance. Try to decrease by a constant. However, when the output of the first source follower starts to decrease, the drain potential of the first transistor has already returned to a high level, so the output of the first source follower remains at a high logic level and does not change. Become.

On the other hand, in the case of normal operation, that is, when the gate potential of the first transistor changes from a low logic level to a high logic level and the first transistor changes from an off state to an on state, the source follower current control The source follower current of the first source follower is controlled to be high by the means, and the output impedance of the first source follower becomes small.Therefore, the drain potential of the first transistor changes from a high level to a low level. sometimes,
The output of the first source follower changes from a high logic level to a low logic level with a small time constant.

In this way, even if the drain potential of the first transistor momentarily decreases due to spike noise, this decrease in potential is not transmitted to the output of the first source follower; Changes in potential are rapidly transmitted to the output of the first source follower.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

In FIG. 1, the sources of transistors Ql and Q2 are commonly connected to the drain of transistor Q3 via a level shift resistor R7. Also, the transistor Ql
, Q2 are commonly connected to the cathode of the level shifting diode D1 via resistors Ret, R, , respectively, and the anode of the diode D1 is connected to the ground terminal v.
11B. On the other hand, the source of transistor Q3 is connected to negative power supply terminal vs3 via resistor R8.

The gate of transistor Q1 is an input terminal C that inputs a signal.
IN, and the gate of the transistor Q2 is connected to the reference voltage terminal v■ on the high potential side. In addition, the gate of transistor Q3 is connected to the constant current circuit reference voltage terminal VCS.
It is connected to the. Transistors Ql, Q2. Q3 and resistance Rn+*Raz+・R? , R, constitute a differential logic section.

The gate of source follower transistor Q4 is at node N1
is connected to the drain of transistor Q1, and the drain of transistor Q4 is connected to ground terminal VDD.

In this invention, source follower transistor Q4
A source follower current control circuit is provided to control the current flowing to the source follower current control circuit.

This source follower current control circuit consists of transistor Q5
and a resistor R3F. transistor Q
The sources of 5 are commonly connected to the negative power supply terminal VSS via a resistor R1F. The drain of the transistor Q5 is connected to the source of the source follower transistor Q4 via a level shift diode D2.

Further, the gate of the transistor Q5 is connected to the drain of the transistor Q3. The output terminal C is connected to the connection point between the cathode of the level shifting diode D2 and the drain of the transistor Q5. Note that the transistors Q1 to Q5 are normally-on type FETs.

Next, the operation of this semiconductor integrated circuit device will be explained.

When the potential of the input terminal CIN is at a low logic level,
Since the transistor Ql is in a cut-off state and the transistor Q2 is in a conductive state, the switching current is 1. is the ground terminal vD
11 to resistor R0, transistor Q2. Resistor R1, transistor Q3. The current flows following resistance R8. The source potential V*(Q5) of the transistor Q5 at this time can be approximated by the following equation.

Vs (Q5) = vm+-vt (Q2) RTI.

-■A (Q5) (1) Here, ■□ is the potential of the reference voltage terminal VR1° on the high potential side, vT (Q2)
is the threshold voltage of the transistor Q2, Rt is the resistance value of the level shift resistor RT, Io is the switching current, and VA(Q5) is the threshold voltage of the transistor Q5.

Further, when the potential of the input terminal CIN is at a high logic level, the source potential V, (Q5) of the transistor Q5 is V3(Q5)2V+s*v, (Ql)-R,1,
−Vy (Q5) (2). here,
V and NH are the potentials of the high logic level signal applied to the input terminal CIN, and V? (Ql) is the threshold voltage of transistor Q1.

Now, considering again the case where the potential of the input terminal CIN is at a low logic level, the source potential V3 of the transistor Q5 (
Q5) is in a low potential state, so the source follower current of source follower transistor Q4 is in a low current state. Therefore, the output impedance seen from transistor Q4 is large.

That is, when the potential of the input terminal CIN is at a low logic level, the transistor Q1 is in the off state and the transistor Q2 is in the on state, so that the source potential of the current source transistor Q5 becomes the above equation (1), and the transistor Q5 becomes It becomes a low current state. Therefore, the output terminal C becomes a high logic level, but at this time, the source current of the transistor Q4 is small, and the transistor Q4 is almost in a cut-off state.

Consider a case where this circuit is irradiated with alpha rays in this state.

Now, since the transistor Q1 is in the off state, the node N
The potential of 1 is at a high level.

At this time, when the transistor Q1 is irradiated with alpha rays, electron-hole pairs are generated in the semi-insulating substrate, and the generated electrons travel with a time constant of several tens to several hundreds of ps due to drift and diffusion. Then, when these electrons are collected in the drain region, the potential of the node N1 drops instantaneously. This drop in potential returns to the original high level by being charged from the ground terminal van via the resistor RDI, but this charging generates spike noise with a pulse width of several hundred ps at the minimum.

In this case, as described above, the source follower transistor Q4 is close to the cutoff state, so if the potential of the node Nl drops momentarily, the gate-source voltage of the transistor Q4 becomes O volts or negative, and it is easily cut off. state. Therefore, the output impedance of the transistor Q4 becomes a very large value, so the potential at the output terminal C falls with a very large time constant. However, when the potential of the output terminal C starts to fall, the potential of the node N1 is already rising, and the gate and source of the transistor Q4 become forward biased, so the potential of the output terminal C becomes a high logic level. .

Therefore, even if spike noise occurs at the node N1 and the node N1 momentarily becomes a low level, the potential of the output terminal C remains at a high logic level and does not fluctuate.

As described above, the response speed of the source follower becomes extremely slow in response to spike noise caused by α rays, but the response speed does not decrease during normal operation.

This is because when the potential of the input terminal CIN changes from a low logic level to a high logic level and the potential of the node N1 changes from a high level to a low level, the gate potential of the transistor Q5 rises and the source follower current ( This is because the output impedance of transistor Q4 becomes low because Isy) is in a high current state. That is, this is because the transistor Q5 can discharge the load more quickly.

In the above embodiment, an example of a one-person gate was shown, but as shown in the second embodiment of FIG. In many cases, the same effect as above can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, even if spike noise due to alpha rays is input to the gate of the source follower, the spike noise is attenuated and transmitted to the output of the source follower by the function of the source follower current control means.
In normal operation when the first transistor changes from off to on, the output of the source follower changes quickly, so alpha rays can be used without increasing power consumption or delay time. This has the effect of improving soft error resistance.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional gate circuit, and FIG. 3 is a logic circuit that combines a conventional gate circuit and a D latch circuit. Figure 4 is a diagram showing another embodiment of the present invention. In the figure, Ql, Q2.Q3.Ql', Ql' are transistors constituting a source-coupled logic circuit, and Q4 is a source follower transistor. , Q5 is a source follower current source transistor constituting a source follower current control circuit, DI and D2 are level shift diodes,
Rt is a level shift resistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The sources of at least the first transistor and the second transistor are commonly connected to a constant current source, the current path is switched by the potential applied to the gate of each transistor, and the drain potential of at least the first transistor is connected to the source. In a semiconductor integrated circuit device comprising a source-coupled logic circuit that is extracted and output by a follower, the source follower current when the first transistor is in an off state is compared to the source follower current when the first transistor is in an on state. A source follower current control means is provided, the source follower current control means is configured to generate a signal obtained by lowering the potential of the common source of the first and second transistors by a level shift resistor connected to the source. What is claimed is: 1. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is configured by inputting the input signal to the gate of a current source transistor.