JPH03130999A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the energy consumption of a redundant selecting circuit by mutually connecting a power source VCC and one end of two fuses, to which a ground potential is impressed respectively through a voltage drop means, and defining the connecting point as an output terminal. CONSTITUTION:When a fuse 2 is cut, the connection between the power source VCC and an output terminal T0 is interrupted and the charge of the terminal T0 is discharged through a fuse 3 by the operation of a transistor Tr5. Then, a signal at an 'L' level is outputted from the terminal T0. At such a time, since a voltage lowered only for the voltage drop of a Tr4 is impressed from the power source VCC to one end of the fuse 2, reconnection caused by the high voltage of a cut part is prevented in advance after cutting the fuse 2. On the other hand, when the fuse 3 is cut, a signal at an 'H' level is outputted from an output terminal T by the operation of the Tr4. Accordingly, a through current to flow from the power source VCC to a ground G can be interrupted without fail and the energy consumption can be reduced.

Description

[Detailed Description of the Invention] [Summary] A redundancy selection circuit that outputs a redundancy signal for selecting a redundant cell of a semiconductor memory device, which can reliably invert the output signal based on the disconnection of a fuse, and has low power consumption. A semiconductor integrated circuit is provided with a control signal generation circuit that generates a control signal based on whether or not a fuse is blown, and one end is connected to a first power supply line through a first voltage drop means. a first fuse connected to the first fuse; and a second fuse, one end of which is connected to the other end of the first fuse, and the other end of which is connected to the second power supply line via a second voltage drop means. and a connection point between the first and second fuses is configured as an output terminal.

[Industrial Field of Application] The present invention relates to a redundancy selection circuit that outputs a redundancy signal for selecting a redundancy cell of a semiconductor memory device based on the disconnection of a fuse.

In a semiconductor memory device, redundant cells are provided in advance among a large number of cells constituting a storage area, and when a defective cell occurs, access to the defective cell is switched to the redundant cell. The switching is performed based on a redundancy signal that is output from a redundancy selection circuit provided in the semiconductor memory device in advance to an address decoder when an address is selected, and the redundancy signal is output based on the cutting of a fuse provided in the redundancy selection circuit. be done.

[Prior Art] In the redundancy selection circuit shown in FIG. 4, one end of the fuse 1 is connected to the power supply vp, and the other end is connected to the output terminals To and N.
It is connected to the drain of the channel MOS transistor Tr1, and the source of the transistor Tr1 is connected to the N-channel MOS transistor Tr1.
It is connected to the drain of the S transistor Tr2, and the source of the transistor Tr2 is connected to the ground G. Further, a power supply Vcc is supplied to the gate of the transistor Trl, and a gate voltage vth slightly higher than the threshold voltage is supplied to the gate of the transistor Tr2.

When the fuse 1 is not cut off, the voltage drop caused by the transistors Trl and Tr2 is sufficiently larger than the voltage drop caused by the fuse 1, so that an output signal of H level approximately equal to the power supply ■p is output from the output terminal To. Further, when the fuse 1 is cut, the transistor Tr1. The charge from the output terminal To is removed by Tr2, and an L level output signal is output from the same output terminal TO.Based on this output signal, the address decoder stops accessing the defective cell and selects a spare cell. ing.

Note that the fuse 1 is disconnected by applying a voltage higher than the normal power supply voltage to the power supply Vp and outputting an H level redundancy selection signal to the gate of the fuse disconnection transistor Tr3 connected to the other end of the fuse 1. This is done by passing a drain current through Tr3.

[Problems to be Solved by the Invention] However, in the redundancy selection circuit as described above, when fuse 1 is not disconnected, the transistor T is disconnected from fuse 1.
r1. Point U occurs during which the power consumption increases because the through current continues to flow through Tr2.

An object of the present invention is to provide a redundant selection circuit which can reliably invert its output signal based on the cutting of a fuse and which has less Vtt power.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. That is, a semiconductor integrated circuit equipped with a control signal generation circuit that generates a control signal based on whether or not a fuse is disconnected has a first power supply line Vcc connected at one end to a first power supply line Vcc via a first voltage drop means 4. a second fuse 3 whose one end is connected to the a end of the first fuse 2 and whose other end is connected to the second power supply line G via the second voltage drop means 5. The connection point between the first and second fuses 2 and 3 is an output terminal TO.

[Operation] When the first fuse 2 is cut off, an L level signal is output from the output terminal To, and when the second fuse 3 is cut off, an H level signal is output from the output terminal To. Therefore,
When an H level or L level signal is output from the output terminal To, the first and second fuses 2.3
Either one of them is disconnected.

[Embodiment 1] An embodiment of a redundancy selection circuit embodying the present invention will be described below with reference to FIG.

The redundancy selection circuit of this embodiment has a P channel M connected to the power supply VCC.
O8) The source of the transistor Tr4 is connected, the drain of the transistor Tr4 is connected to one end of the first fuse 2, and the other end of the first fuse 2 is connected to the output terminal T.
o and one end of the second fuse 3. The other end of the second fuse 3 is N channel M
The transistor Tr5 is connected to the drain of the OS transistor Tr5, and the source of the transistor Tr5 is connected to the ground G4.The transistor Tr4 has its gate connected to the ground G and is always kept on, and the transistor Tr5 has its gate connected to the ground G. It is connected to the power supply VCC and is always kept on. Further, each of the first and second fuses 2 and 3 is cut by laser beam irradiation.

As shown in FIG. 3, the redundancy selection circuit configured in this way is provided with one circuit for one address as the ROM section 6 and connected to the redundancy comparison circuit 7, which is connected to the memory cell array 8. When the address selection signal is output, an external address signal at H level is input. When H level signals are input to both input terminals of the redundancy comparison circuit 7, the redundancy selection circuit 7 outputs an H level output signal to the redundancy determination circuit 9. A non-redundant address predecoder 10 and a redundant address predecoder 11 are connected to the redundancy determination circuit 9, and when an H level signal is input from the redundancy selection circuit 7, the non-redundant address predecoder 10 is connected to the redundancy determination circuit 9.
is made inactive, and the redundant address predecoder 11 is made active. Therefore, in this state, a redundant cell is selected in the memory cell array 8, and when an L level signal is output from the redundancy selection circuit 7, the state is reversed.

Now, in the redundancy selection circuit configured as described above, when the first fuse 2 is cut off, the connection between the power supply Vcc and the output terminal To is cut off, and the charge on the output terminal To is transferred to the second one by the operation of the transistor Tr5. Since it is pulled out via the fuse 3, an L level signal is immediately output from the same output terminal To.

At this time, a voltage lower than the power supply VCC by the voltage drop of the transistor Tr4 is applied to one end of the first fuse 2, so that reconnection due to the high voltage at the disconnected part after the first fuse 2 is disconnected is prevented. It is prevented.

On the other hand, when the second fuse 3 is cut, the transistor T
Based on the operation of r4, an H level signal is output from the output terminal To.

Therefore, in this redundancy selection circuit, from its output terminal TO
When outputting a level or L level signal,
Since one of the first and second fuses 2.3 is always disconnected, the through current flowing from the power supply Vcc force to the ground G can be reliably interrupted.

Since such a redundancy selection circuit is provided in the ROM section 6, one circuit for each address, by adopting the above configuration, consumption can be significantly reduced.

Note that the transistor Tr4. A resistor can also be used in place of Tr5.

[Effects of the Invention] As detailed above, the present invention makes it possible to reliably invert the output signal based on the actual location of the fuse, and to significantly reduce the power consumption of large-scale semiconductor storage devices. This provides an excellent effect of providing a redundant selection circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of this invention. FIG. 2 is a circuit diagram showing a redundancy selection circuit embodying the invention. FIG. 3 is a block diagram showing a semiconductor integrated circuit using the redundancy selection circuit. The figure is a circuit diagram showing a conventional example related to the present invention. In the figure, 2 is a first fuse, 3 is a second fuse, 4 is a first voltage drop means, and 5 is a second voltage drop means. Vcc is the first power line, and G is the second power line.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit equipped with a control signal generation circuit that generates a control signal based on whether or not a fuse is blown, the semiconductor integrated circuit having one end connected to a first voltage drop via a first voltage drop means (4). a first fuse (2) connected to the power supply line (Vcc), one end connected to the other end of the first fuse (2), and the other end connected to the second voltage drop means (5). and a second fuse (3) connected to the second power supply line (G) through the fuse, and the connection point of the first and second fuses (2, 3) is an output terminal (T_0). A semiconductor integrated circuit characterized by: