JPH03106076A - Manufacture of semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To improve a semiconductor nonvolatile memory in manufacturing yield when it is manufactured in a double self-aligned method by a method wherein a floating gate formed of a first semiconductor layer is formed in a self-alignment manner to a control gate. CONSTITUTION:A first resist pattern 9 is formed on an etching mask layer 8, and the etching mask layer 8 and a layer 7 including a second semiconductor layer are successively etched using the first resist pattern 9 as a mask to form a control gate CG formed of the layer 7 which includes the second semiconductor layer. The surface of a part formed of a first semiconductor layer excluding a pattern 5 is covered with a second resist pattern 10, and the pattern 5 formed of the first semiconductor layer is etched using the first resist pattern 9 as a mask to form a floating gate FG formed of the first semiconductor layer as self-aligned with the control gate CG. By this setup, a nonvolatile memory of this design can be improved manufacturing yield.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is applied to the production of semiconductor nonvolatile memory having a memory cell structure in which a control gate is stacked on a floating gate. Regarding the method.

[Summary of the Invention] The present invention provides a method for manufacturing a semiconductor nonvolatile memory having a memory cell having a structure in which a control gate is stacked on a floating gate. a step of forming a layer including at least a second semiconductor layer on the pattern and the semiconductor substrate through an insulating film, and a step of forming a pattern including at least the first semiconductor layer; forming an etching mask layer having different etching characteristics from the first semiconductor layer on the layer including the second semiconductor layer on the pattern; forming a first resist pattern on the etching mask layer; forming a control gate made of a layer including a second semicircular layer by sequentially etching the layer including the etching mask layer and the second semiconductor layer using the resist pattern as a mask;
The surface of the portion other than the pattern made of the semiconductor layer is covered with a second resist pattern, and the pattern made of the first semiconductor layer is etched using the first resist pattern as a mask in a self-aligned manner with respect to the control gate. forming a floating gate made of the first semiconductor layer. Thereby, it is possible to improve the manufacturing yield when manufacturing semiconductor nonvolatile memories using the double cell line method.

[Prior Art] Conventionally, as this type of semiconductor non-volatile memory, E P
R O M (Erasable and Progr.
ammable Read Only Memory)
and E E P R O M (Electrical
y Erasable and Programmable
Read Only Memory). In recent years, in order to increase the integration density and improve the write characteristics of these EPROMs and EEPR○Ms, a manufacturing method called the double self-line method, in which a control gate and a floating gate can be formed in a self-aligned manner, has been developed. Many methods are used.

FIGS. 2A to 2H show a conventional method of manufacturing an EFROM of the double self-line type. According to this method, as shown in FIG. 2A, first, for example, p-type silicon (Si) is
Base! Is there a field insulating film for isolation between elements, such as a StOt film, on the surface of gi101? 02 is selectively formed, and a P'' type channel stopper region 103, for example, is formed under the field insulating film 102. Next, a gate insulating film 104 such as a SiO2 film is formed on the surface of the active region surrounded by the field insulating film 102. Next, the entire surface is coated with polycrystalline St, for example, by the CVD method.
After forming a polycrystalline Si film and doping the polycrystalline Si film with an impurity such as phosphorus (P) to lower its resistance, the polycrystalline Si film is
The i-film is patterned into a predetermined shape by etching. Reference numeral 105 indicates a polycrystalline Si film patterned in this manner. The width of this polycrystalline Si film 105 in the direction perpendicular to the cross section shown in FIG. 2A is the same as that of the floating gate FC'' described later.

Next, as shown in FIG. 2B, the surface of the polycrystalline St film 105 is coated with, for example, Sin. A film-like insulating film (coupling insulating film) 106 is formed.

Next, as shown in FIG. 2C, a second layer of polycrystalline Si film 107 is formed on the entire surface by, for example, the CVD method, and then this polycrystalline Si film 107 is doped with an impurity such as P. Lower resistance. Thereafter, a resist pattern 10 of a predetermined shape is formed on this polycrystalline SL film 107 by lithography.
form 8.

Next, using this resist pattern 108 as a mask, polycrystalline silicon is etched by, for example, reactive ion etching (RIE).
The T film 107 is anisotropically etched in a direction perpendicular to the substrate surface to form a control gate CG' as shown in FIG. 2D.
and a gate electrode G' for a MOS transistor in a peripheral circuit section, etc., is formed.

Next, as shown in FIG. 2E, after covering the surface of the peripheral circuit section with a second layer resist pattern 109, for example,
The insulating film 106 is anisotropically etched in a direction perpendicular to the substrate surface using the IE method.

Next, using the resist pattern 108 as a mask, for example, R
The polycrystalline Si film 105 is anisotropically etched in a direction perpendicular to the substrate surface using the IE method. As a result, floating gate FC' is formed in self-alignment with control gate cG', as shown in FIG. 2F. After this, the resist patterns 108 and 109 are removed.

Next, as shown in Figure 2G, the floating game
Gate insulating film 10 in parts other than G' and gate electrode G'
6 is removed by etching.

Next, by performing thermal oxidation, as shown in FIG. 2H, the p-type St substrate 101 exposed by the above etching is
While forming the gate insulating film 104 again on the surface of
Control gate CG'Floating game}FC'
Then, an insulating film 110 such as a SiOt film is formed on the surface of the gate electrode G'. Next, control gate C
Using G', floating gate FC', and gate electrode G' as masks, an n-type impurity such as arsenic (As) is ion-implanted into p-type Si substrate 101. As a result, for example, the n°-type source region 11'L and drain region 112 are formed in a self-aligned manner with respect to the control gate CG' and the floating gate FG', and, for example, the n-type source region 113 The drain nozzle region 114 is formed in a self-aligned manner with respect to the gate electrode G'. A memory transistor is formed by the control gate CG', the floating gate FC', the source region 111, and the drain region 112. Further, the gate electrode G', the source region 113, and the drain region 114 form a MOS transistor for a peripheral circuit section. Thereafter, an interlayer insulating film 115 is formed on the entire surface by, for example, a CVD method.

[Problem to be solved by the invention]

In the conventional double-self line type EPROM manufacturing method described above, two layers of resist (double resist) are used to form the control gate CG' and the floating gate FG', so the following steps are taken. A problem arises.

That is, during actual EFROM manufacturing, the second layer resist pattern 109 may be formed out of position, or the resist pattern 109 may be formed out of position due to poor development.
09 shape defects may occur. In such a case, it is conceivable to remove the resist pattern 109 once and regenerate it, but this resist pattern 1
When attempting to remove 09, the first layer resist pattern 108 is also removed at the same time. As a result, the second
When the first polycrystalline Si film 105 is etched in the step shown in FIG. F, the control gate CG' is also etched. Therefore, the second layer resist pattern 10
9 can be said to be practically impossible to reproduce. For these reasons, defects in the second-layer resist pattern 109 have conventionally led to a decrease in the manufacturing yield of EPROMs.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory that can improve the manufacturing yield when manufacturing a semiconductor nonvolatile memory using the double-self line method.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor nonvolatile memory having a memory cell having a structure in which a control gate (CC) is stacked on a floating gate (FG). A pattern consisting of the first semiconductor layer (
5) and forming an N (7) including at least a second semiconductor layer on the pattern (5) consisting of the first semiconductor layer and the semiconductor substrate (1) with an insulating film (6) interposed therebetween. and a pattern consisting of at least the first semiconductor layer (
5) An etching mask layer (8) having different etching characteristics from the first semiconductor layer on the layer (7) including the second semiconductor layer above.
), forming a first resist pattern (9) on the etching mask layer (8), and using the first resist pattern (9) as a mask, etching the etching mask layer (8).
) and the layer (7) including the second semiconductor layer to form a control gate (CG) consisting of the layer (7) including the second semiconductor layer; The control gate is formed by covering the surface of the portion other than the pattern (5) with a second resist pattern (10), and etching the pattern (5) made of the first semiconductor layer using the first resist pattern (9) as a mask. A floating gate (FC) made of a first semiconductor layer is formed in a self-aligned manner with respect to (CG).

For example, a polycrystalline SR film doped with impurities is used as the first semiconductor layer and the second semiconductor layer. In this case, as the etching mask layer (8), a material having etching resistance is used when etching the polycrystalline St film. Specifically, this etching mask N(8) is made of, for example, tungsten (W), molybdenum (Mo
), titanium (Ti), tantalum (Ta), and other high-melting point metal films, for example, Si○2 film, SiffN41, etc. can be used.

As the layer (7) including at least the second semiconductor layer, it is possible to use, for example, a polycrystalline SF film doped with impurities, a polycide film in which a refractory metal silicide film is formed on the polycrystalline Si film, or the like. can.

[Effect]

According to the above means, the second resist pattern (10
) is formed, an etching mask layer (8) is formed on the control game (CG). Therefore, when it is necessary to reproduce this second resist pattern (10), this second resist pattern (10)
Even if the first resist pattern (9) is removed at the same time when the resist pattern (CG) is removed, the etching mask layer (8) remains on the control gate (CG).
The control gate (CC) can be prevented from being etched during etching to form the floating gate (FC).

Then, by etching the pattern (5) made of the first semiconductor layer using this etching mask layer (8), a floating gate (FC) can be formed in a self-aligned manner with respect to the control gate (CG). can.

Note that by using a low resistance material such as a high melting point metal film as the etching mask layer (8), it is possible to lower the resistance of the control gate (CG).

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This embodiment is an example in which the present invention is applied to manufacturing a double-self line type EFROM. In addition, in all the drawings of the embodiment, the same parts are given the same reference numerals.

1A to 1H are EPROs according to an embodiment of the present invention.
The manufacturing method of M is shown below.

In this embodiment, the steps up to the step shown in FIG.
The process proceeds in the same manner as shown in Figures A and 2B. That is, as shown in FIG. 1A, first, for example, a P-type Si substrate 1 is
A field insulating film 2 for device isolation, such as a SiO2 film, is selectively formed on the surface of the semiconductor device, and a p-type channel stopper region 3, for example, is formed under the field insulating film 2. Next, for example, St. ．． A gate insulating film 4 like a film is formed. Next, a polycrystalline Si film is formed by, for example, the CVD method, this polycrystalline St film is doped with an impurity such as P to lower its resistance, and then this polycrystalline Si film is patterned into a predetermined shape by etching. ning. Reference numeral 5 indicates a polycrystalline Si film patterned in this manner.

Next, as shown in FIG. 1B, the surface of the polycrystalline SilI5 is coated with, for example, Sin. A film-like insulation WA (coupling insulation 11!) 6 is formed.

Next, as shown in FIG. 1C, a polycrystalline Si film 7 is formed on the entire surface by, for example, the CVD method, and the polycrystalline St film 7 is doped with an impurity such as P to lower the resistance. A high melting point metal film 8 such as W, Mo, or TiTa is formed on this polycrystalline Si film 7 by, for example, sputtering or vacuum evaporation. Thereafter, a resist pattern 9 having a predetermined shape is formed on this high melting point metal film 8 by lithography.

Next, using this resist pattern 9 as a mask, the high melting point metal film 8 and the polycrystalline St film 7 are anisotropically etched in a direction perpendicular to the substrate surface by, for example, RIE, to form a two-layer film as shown in FIG. 1D. A control gate CG made of a second polycrystalline Si film and a gate electrode G for a MOSI transistor such as a peripheral circuit portion made of a first polycrystalline Si film are formed. A high melting point metal film 8 remains on these control gates CG and gate electrodes G. Next, as shown in FIG. 1E, after covering the surface of the peripheral circuit portion etc. with a second layer resist pattern 10,
The insulating film 6 is anisotropically etched in a direction perpendicular to the substrate surface using the E method.

Next, using the resist pattern 9 as a mask, for example, RIE is performed.
The first polycrystalline Si film 5 is anisotropically etched in a direction perpendicular to the substrate surface using a method. As a result, as shown in FIG. 1F, the floating game }FC is implemented in a self-consistent manner with respect to the control game 1-CG. After this,
Resist patterns 9 and 10 are removed.

Next, as shown in FIG. 1G, the floating game}F
The portions of the gate insulating film 4 other than C and the gate electrode G are removed by etching.

Next, by performing thermal oxidation, as shown in FIG. Then, an insulating film 11 such as a StO1 film is formed on the surface of the gate electrode G. Next, using the control gate CG, floating gate FC, and gate electrode G as masks, p
An n-type impurity such as As is ion-implanted into a type Si substrate 1 . As a result, for example, the n-type source region 12 and drain region 13 are formed in a self-aligned manner with respect to the control gate CG and floating gate FG, and, for example, the n-type source region 14 and drain region 15 are formed in a self-aligned manner with respect to the control gate CG and floating gate FG. It is formed in a self-aligned manner with respect to the gate electrode G. Control gate CG, floating gate FC, source region 12 and drain region 1
3 forms a memory transistor. Further, the gate electrode G1, the source region 14, and the drain region 15 form a MOS transistor for a peripheral circuit section, etc.

Next, for example, a phosphosilicate glass (PSG) film or St
An interlayer insulating film 16 such as an OT film is formed.

Thereafter, the target EPROM is completed through a process of forming contact holes, aluminum (A1) wiring, etc.

As described above, according to this embodiment, the second layer of polycrystalline S
A high melting point metal film 8 that is resistant to the etching of the polycrystalline St film is formed on the T film 7, and these high melting point metal film 8 and the polycrystalline St film 7 are etched using the resist pattern 9 as a mask. , the structure is such that a high melting point metal film 8 is formed on the control gate CG. Even when the second layer resist pattern 10 is formed, the high melting point metal film 8 remains on the control gate CG. Therefore, when it is necessary to reproduce the second layer resist pattern 10, even if the first layer resist pattern 9 is also removed at the same time when the second layer resist pattern 10 is removed, the control game C
Since the high melting point metal film 8 remains on G, the first layer of polycrystalline St is used to form the floating gate FG.
When etching the film 5, this control gate CG
can be prevented from being etched. This makes it possible to improve the manufacturing yield of EPROMs.

Furthermore, since a low resistance high melting point metal film 8 is formed on the control gate CG and the gate electrode G, the resistance of these control gates CG and gate electrode G is reduced by this high melting point metal film 8. be able to.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, in the embodiment described above, it is also possible to perform heat treatment after forming the high melting point metal film 8 to silicide the high melting point metal film 8. Furthermore, in the above-described embodiments, the case where the present invention is applied to the manufacture of EPROMs has been described, but the present invention can also be applied to the manufacture of EEPROMs.

[Effects of the Invention] Since the present invention is configured as described above, it is possible to improve the manufacturing yield when semiconductor nonvolatile memories are manufactured by the double-cell line method.

[Brief explanation of drawings]

1A to 1H are EPROs according to an embodiment of the present invention.
Cross-sectional views for explaining the manufacturing method of M in the order of steps, FIGS. 2A to 2H are EPs of the conventional double self-line method.
FIG. 3 is a cross-sectional view for explaining the ROM manufacturing method step by step. Explanation of main symbols in the drawings 1: p-type St substrate, 2: field insulating film, 4: gate insulating film, 5: first layer polycrystalline Si film, 6: insulating film,
7: Second layer polycrystalline SilpJ, 8: High melting point metal film, 9: First layer resist pattern, 10: Second layer resist pattern, 12.14: Source region,
13, 15: drain region, CG: control gate, FG: floating gate.

Claims (1)

[Claims] In a method for manufacturing a semiconductor nonvolatile memory having a memory cell having a structure in which a control gate is stacked on a floating gate, a pattern consisting of a first semiconductor layer is formed on a semiconductor substrate with a gate insulating film interposed therebetween. forming a pattern made of the first semiconductor layer and a layer including at least a second semiconductor layer on the semiconductor substrate with an insulating film interposed therebetween; and a pattern made of at least the first semiconductor layer. forming an etching mask layer having etching characteristics different from those of the first semiconductor layer on the layer including the second semiconductor layer above; forming a first resist pattern on the etching mask layer; forming a control gate made of a layer including the second semiconductor layer by sequentially etching the etching mask layer and the layer including the second semiconductor layer using the first resist pattern as a mask; The surface of the portion other than the pattern made of the semiconductor layer is covered with a second resist pattern, and the pattern made of the first semiconductor layer is etched using the first resist pattern as a mask to achieve self-alignment with the control gate. and forming a floating gate made of the first semiconductor layer.