JPH03102760U - - Google Patents

Info

Publication number
JPH03102760U
JPH03102760U JP1024690U JP1024690U JPH03102760U JP H03102760 U JPH03102760 U JP H03102760U JP 1024690 U JP1024690 U JP 1024690U JP 1024690 U JP1024690 U JP 1024690U JP H03102760 U JPH03102760 U JP H03102760U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
lead terminal
circuit board
output electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1024690U
Other languages
Japanese (ja)
Other versions
JPH0744042Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990010246U priority Critical patent/JPH0744042Y2/en
Publication of JPH03102760U publication Critical patent/JPH03102760U/ja
Application granted granted Critical
Publication of JPH0744042Y2 publication Critical patent/JPH0744042Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案における混成集積回路装置説明
図、第2図は本考案における出力電極と配線パタ
ーンとの接続説明図、第3図は本考案における固
定用リード端子と配線パターンとの接続説明図、
第4図は本考案における混成集積回路装置の取り
付け説明図、第5図は従来例における混成集積回
路装置の取り付け説明図である。 1……混成集積回路装置、2……回路基板、3
……出力電極、4……固定用リード端子、5……
マザーボード、6……配線パターン、7……半田
、8……スルーホール、9……IC、10……モ
ールド樹脂。
Fig. 1 is an explanatory diagram of the hybrid integrated circuit device in the present invention, Fig. 2 is an explanatory diagram of the connection between the output electrode and the wiring pattern in the present invention, and Fig. 3 is an explanatory diagram of the connection between the fixing lead terminal and the wiring pattern in the present invention. figure,
FIG. 4 is an explanatory diagram of the installation of the hybrid integrated circuit device according to the present invention, and FIG. 5 is an explanatory diagram of the installation of the hybrid integrated circuit device in the conventional example. 1... Hybrid integrated circuit device, 2... Circuit board, 3
...Output electrode, 4...Fixing lead terminal, 5...
Motherboard, 6...Wiring pattern, 7...Solder, 8...Through hole, 9...IC, 10...Mold resin.

Claims (1)

【実用新案登録請求の範囲】 ICおよびチツプ部品等を搭載した回路基板2
と、 当該回路基板2の一端部の少なくとも一側に露
出して設けられた複数の出力電極3と、 当該出力電極3の少なくとも二つのシングルイ
ンライン型混成集積回路装置1をマザーボード5
に固定する固定用リード端子4と、 からなることを特徴とするシングルインライン型
混成集積回路装置。
[Scope of claim for utility model registration] Circuit board 2 equipped with IC and chip parts, etc.
a plurality of output electrodes 3 exposed and provided on at least one side of one end of the circuit board 2; and at least two single in-line hybrid integrated circuit devices 1 of the output electrodes 3 are mounted on a motherboard 5.
A single in-line type hybrid integrated circuit device comprising: a fixing lead terminal 4 fixed to a fixed lead terminal 4;
JP1990010246U 1990-02-06 1990-02-06 Single in-line type hybrid integrated circuit device Expired - Lifetime JPH0744042Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990010246U JPH0744042Y2 (en) 1990-02-06 1990-02-06 Single in-line type hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990010246U JPH0744042Y2 (en) 1990-02-06 1990-02-06 Single in-line type hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPH03102760U true JPH03102760U (en) 1991-10-25
JPH0744042Y2 JPH0744042Y2 (en) 1995-10-09

Family

ID=31513828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990010246U Expired - Lifetime JPH0744042Y2 (en) 1990-02-06 1990-02-06 Single in-line type hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0744042Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61188302U (en) * 1985-05-15 1986-11-25
JPS63170967U (en) * 1987-04-27 1988-11-07

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61188302U (en) * 1985-05-15 1986-11-25
JPS63170967U (en) * 1987-04-27 1988-11-07

Also Published As

Publication number Publication date
JPH0744042Y2 (en) 1995-10-09

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