JPH03101341A - Data collection system for packet exchange equipment - Google Patents

Abstract

PURPOSE:To efficiently collect state information by permitting respective storage parts to transmit state information including the presence or absence of a transmission packet to collection control buses to a bus control part and permitting the bus control part to discriminate state information of respective storage parts, which are collected from the collection control buses, and to inform a packet exchange control part of it. CONSTITUTION:When respective storage parts 4 receive accumulation state information and transfer request information on the packet transmitted from a terminal or a transmission line 5, they store information in a buffer. The storage parts 4 transfer state information through the storage control buses 3 independent of input buses 1 and output buses 2 for the packet. Information are collected by the control of the collection control part 63 of the bus control part 6. Then, the packet exchange control part 11 executes a judgement processing and response information corresponding to a transfer request is transmitted to transfer buffers 9, which execute the transfer operation of the packet and output it to output packet transfer lines 8. Thus, the state of many storage parts can be collected at high speed.

Description

[Detailed Description of the Invention] [Summary] A plurality of bus control units are provided to which a pair of input packet transfer paths and a plurality of output packet transfer paths are connected, and the plurality of input packet transfer paths and the plurality of output packet transfer paths are arranged in a lattice. A data collection method for a packet switching device in which the two packet transfer paths are arranged in the form of a pattern, and the two packet transfer paths are connected via a transfer buffer provided at the intersection thereof, and each transfer buffer is controlled by a packet switching control unit connected by a control bus. In this regard, there is provided a data collection method for a storage section of a packet switching device that can efficiently collect status information including transfer requests of a large number of terminals or transmission line storage sections provided outside a packet switch and connected to a bus. With the aim of transmits status information including the presence or absence of transmission packets to the collection control bus to the bus control unit, and the bus control unit determines the status information of each storage unit collected from the collection control bus and sends the status information to the packet exchange control unit. Configure to be notified.

[Industrial Application Fields] The present invention is provided with a plurality of bus control units to which a pair of input packet transfer paths and a plurality of output packet transfer paths are connected, and which connects the plurality of input packet transfer paths and the plurality of output packet transfer paths in a grid. The present invention relates to a data collection method for a packet switching device having a packet switching control section arranged in the form of a plurality of packets, the two packet transfer paths being connected via a transfer buffer placed at the intersection thereof, and a packet switching control section connected to each transfer buffer by a control bus. .

In recent years, various types of data have come to be transmitted using packet 7) switching networks. In this packet switching technology,
A method has been proposed in which the packet exchange switch is configured with a grid-like matrix switch, and a transfer buffer is provided at each intersection to transfer packets.

In contrast to this method, the transfer control method of a high-speed packet switching switch is the same as that of this application, which prevents packet blocking in the transfer buffer without increasing the memory capacity of the transfer buffer and enables reduction of hardware scale. It was previously proposed by the applicant.

On the other hand, the input/output ports of the matrix switch of such high-speed packet switching equipment are connected to input/output buses that are connected to a large number of terminals or transmission line accommodation units connected to the outside of the switch. The packet transmitted from the switch is transferred into the switch under the control of the packet transfer control unit and outputted via the transfer buffer. The packet output from the switch is output from the packet transfer control unit to the output bus, and transferred to the destination terminal or transmission path accommodation unit.

The packet transfer control section described above needs to perform control to receive and receive transmission packets from a plurality of terminals or transmission lines, and transmit control information for switch control to the packet switching control section. In this case, it is desired to transmit and receive control signals quickly and efficiently.

[Prior Art] FIG. 11 is a basic configuration diagram of a conventional example, which is a method previously proposed by the above-mentioned applicant of the present invention (filed as a "transfer control method for packet switching switches"), and FIG. 12 is a diagram showing the basic configuration of a conventional example. FIG. 3 is a diagram showing a frame format on a packet transfer path of a switch.

In FIG. 11, 100 is a packet transfer control unit;
1 and 102 are a reception packet transfer control unit and a transmission packet transfer control unit provided in pairs in each packet transfer control unit;
03 is an input packet transfer path, 104 is an output packet transfer path, 105 is a transfer buffer provided at each intersection of the packet transfer path, 106 is a packet exchange control unit connected to each transfer buffer by a control bus, and 107 is a control bus. represents.

To outline the operation, when a packet is input from the outside to each packet transfer control unit 1゜O, the received packet transfer control unit 1
01, and from there, the request frame is sent out at regular intervals to all transfer buffers 105 connected via the corresponding input packet transfer path 103. The format of the request frame is shown in A in FIG. 12, and first contains status information indicating the state (whether or not the packet can be received) of the transmit packet transfer control unit 102 that is paired with the transfer control unit 101. , transfer request information indicating the transfer destination of the packet that the received packet transfer control unit 101 is about to transfer, and packet information (transmission became possible due to the previous request).

All the transfer buffers 105 connected to the input packet transfer path 103 separate the status information and transfer request information from the packet information, hold the status information and transfer request information, and transfer the packet information via the buffer. A switching operation is performed, and the packet is output to the target output packet transfer path 104.

The status information and transfer request information held in each transfer buffer 105 are sequentially read out by each control bus 107 according to instructions from the packet switching control unit 106, and the transfer request status and transmission information from all received packet transfer control units 101 are The status information of the packet transfer control unit 102 is updated based on this input information. Here, the status of the transmission packet transfer control unit 102 in response to the transfer request is checked, it is determined whether transfer is permitted or not in response to the request, and response information representing the result is notified to the transfer buffer 105 from the corresponding control bus 107. do.

Transfer buffer 105 transfers the response information from output packet transfer path 104 to transmission packet transfer control section 102 . On the other hand, if the packet input from the manual packet transfer path 103 is permitted to be transferred by the packet switching control unit 106, the timing is controlled so that the packet is transferred to the output packet transfer 8104 through the corresponding transfer buffer 105. Response information is transferred before packet information. The format of the response frame sent from the transfer buffer 105 to the output packet transfer path is as shown in B in FIG.

When the transmission packet transfer control unit 102 receives a response frame, the response information therein is supplied to the paired reception packet transfer control unit 101 (along with the status information of the transmission packet transfer control unit), and the response information in the response frame is supplied to the reception packet transfer control unit 101 (along with the status information of the transmission packet transfer control unit), and the response information in the response frame is supplied to the reception packet transfer control unit 101 (along with the status information of the transmission packet transfer control unit), and the response information therein is supplied to the reception packet transfer control unit 101 (along with the status information of the transmission packet transfer control unit). Sending control is performed, and packet information is transferred to the outside from the sending packet transfer control unit 102.

[Problem to be Solved by the Invention 1] In the above conventional system, the packet transfer control unit receives transfer request information from the reception packet transfer control unit (information of the transmission packet transfer control unit) and status information of the transmission packet transfer control unit. is sent to the packet switching control unit via the input packet transfer path and transfer buffer, but the receiving packet transfer control unit that makes the transfer request is sent from outside the switch to a large number of terminals or transmission lines via the bus. It is necessary to know the information about the storage unit's transfer request.

In other words, a bus for inputting and outputting packets is provided outside each packet transfer control unit provided in a matrix (a lattice arrangement of input packet transfer paths and output packet transfer paths), and a terminal or a transmission path is accommodated in the bus. A plurality of accommodating units are connected, and in order to set the transfer request information in the above-mentioned request frame from the packet transfer control unit, it is necessary to read the transfer request information from each accommodating unit one by one. However, as the scale increases, it takes time to collect information from all storage units, and by the time the collection is complete, the status has changed, making it impossible to manage the current status.

The present invention provides data in a storage section of a packet switching device that is provided outside a bus control section of a packet switch and can efficiently collect status information including transfer requests of a large number of terminals connected to a bus or a storage section of a transmission path. The purpose is to provide a collection method.

[Means to solve the problem] FIG. 1 is a basic configuration diagram of the present invention.

In Figure 1, 1 and 2 are input and output buses for packet transfer that connect multiple storage units and the bus control unit, and 3 is a bus control unit that connects each storage unit in tandem (relay format). A collection control bus provided physically (by providing a dedicated bus) or logically (by setting a dedicated channel on the human/output bus, etc.) to transfer status information; 4 is a bus control bus that accommodates terminals or transmission lines; 5 is a terminal or a transmission path (only the terminal is shown in the figure); 6 is a storage section provided between the terminal or transmission path and the packet switch; The bus control unit (conventional packet (corresponding to the transfer control unit), 61
゜ε2 is an input bus control section (including the function of the reception packet transfer control section of the conventional example) and an output bus control section (including the function of the transmission packet transfer control section of the conventional example), which are provided as a pair in the bus control section. 63 is a collection control unit that is connected to the collection control bus 3 and controls the collection of information from the storage unit; 7.8 is an input packet transfer path and an output packet transfer provided in pairs, one for each bus control unit 6; 9 is a plurality of transfer buffers (00 to MN) provided at each intersection of the packet transfer path; 10 is a control bus connecting the packet switching control unit and the transfer buffer;
Reference numeral 1 represents a packet exchange control section (separately provided corresponding to each control bus, or a common control section provided) connected by a transfer buffer 9 and a control bus 10 connected to each output packet transfer path.

In addition to an input/output bus for transferring packet information between a plurality of storage units and a bus control unit, the present invention connects physical or logical control lines in tandem between each storage unit and the bus control unit. Then, the status information of each accommodation section is notified to the bus control section using the control line.

[Operation] In the configuration shown in FIG. 1, the input packet transfer path 7 constituting the matrix switch. Output packet transfer path 8. Transfer buffer 9. The packet exchange control section 11 and the control bus 10 have the same configuration as the conventional example (see FIG. 11), and the input bus control section 61. The functions of the configuration (configuration corresponding to the conventional reception packet transfer control section and transmission packet transfer control section) related to switch control (transfer fee via transfer buffer) in the output bus control section 62 are as explained in the above conventional example. The content is the same as the above, and the explanation of its effect will be omitted.

The operation of transfer control between the storage section 4 and the bus control section 6 will be explained below.

When each storage unit 4 receives packet storage status information and transfer request information transmitted from a terminal or a transmission path (hereinafter simply referred to as a terminal) 5, the storage unit 4 stores the information in a buffer (not shown). The storage unit 4 sends the status information to the input bus l for packets.

Transfer via the output bus 2 and an independent collection control bus 3. Collection of this information is performed under the control of the collection control section 63 of the bus control section 6.

Since the collection control buses 3 are connected in tandem, if the one closest to the bus control unit 6 is defined as the upstream, status information flows from downstream to upstream, and its operation is controlled by the collection control unit 6.
It is executed periodically by commands from 3. At this time, the storage unit 4 that has received the information from the adjacent downstream storage unit compresses its own information and notifies it to the adjacent upstream storage unit 4 connected by the collection control bus 3. By repeating this process, the collection control section 63 of the bus control section 6 will have information on all the storage sections 4.

In response to an instruction from the collection control unit 63, each storage unit 4 writes its own current state information after the information outputted by the storage unit in the previous order in accordance with the connected position.

The collection control unit 63 of the bus control unit 6 manages the status information, and transfer request information is stored as the status of the paired output bus control unit (packets can be received from the output packet transfer path 8), as in the conventional example. ) and the packet that is permitted to be transferred are sent to the input packet transfer path 7 as a request frame format, and are sent to the transfer buffer 9 . The data is transferred to the packet switching controller 11 via the control bus IO.

The packet switching control unit 11 performs judgment processing, and the response information corresponding to the transfer request is sent to the transfer buffer 9, the transfer buffer 9 executes the packet transfer operation, and the output packet transfer path is transferred using the same response frame format as before. 8 is output.

The packet and response information are input to the bus control unit 6,
The packet information is sent to the output bus 2 and transferred to the terminal 5 via the storage unit 4, and the response information is sent to the input bus control unit 61 (
(corresponding to the conventional input packet transfer control unit),
Transfer control of packets to the input packet transfer path 7 is performed.

[Example] Of the respective components shown in the basic configuration diagram of FIG. 1, input packet transfer path 7, output packet transfer path 8, which constitutes a packet switch. Transfer buffer 9. The configurations of the control bus 10 and packet switching controller 11 and the configuration regarding switch control within the bus controller 6 are the same as those of the conventional system (FIG. 11).
The following description describes an embodiment of a storage unit and a bus control unit implementing the data collection method of a packet switching device according to the present invention.

Fig. 2 is a connection diagram of the accommodating section and the bus control section, Fig. 3 is an embodiment of the configuration of the receiving circuit of the accommodating section, Fig. 4 is an embodiment of the configuration of the transmitting circuit of the accommodating section, and Fig. 5 6 shows the data format on the acquisition control bus, FIG. 7 shows the configuration of the acquisition control circuit in the bus control section, and FIG. 8 shows the state of the bus control section. An example configuration diagram of the information table, FIG. 9 is an example configuration diagram of the human-powered bus control section,
FIG. 10 is a block diagram of an embodiment of the output bus control section.

In the connection configuration diagram of the accommodating section and the bus control section in Fig. 2, 1
-6 represent the same things as in FIG. 1, and 41 in the housing section 4,
4 is a filter circuit section, 42 is a receiving circuit section, 43 is a transmitting circuit section, 64 in the bus control section 6 is a collection control circuit section, 6
5 is a status information table for each storage section. The collection control section 64 and the status information table 65 constitute the collection control section 63 in FIG. Furthermore, the node control unit 6o
controls the status information table 65 of the plurality of collection control units 63 (reading and writing control).

In FIG. 2, transmission packets from various terminals and transmission lines 5 are input to the receiving circuit section 42 of the corresponding storage section 4 and stored in a buffer, and the status information is stored on the collection control path line 3 (first
(corresponding to the acquisition control bus in the figure) by timing operation in the filter circuit section 41, the transmission packet is sent from the reception circuit section 42 to the input bus 1, and the reception packet is input from the output bus 2 to the transmission circuit section 43. (detects that the destination is your own device and imports it).

Each accommodating unit 4 adds the state information of its own terminal to the filter circuit unit 41 to the data received from the adjacent downstream accommodating unit (on the left side of the figure), and sends the data to the upstream accommodating unit, sequentially. The information is added, and the status information of all storage units 4 connected to the same bus control unit 6 is input to the collection control circuit unit 64 of the bus control unit 6, and is processed to create a status information table 65 for each storage unit. is stored in Information such as a transfer request is extracted from the status information from the input bus control unit 61 and used for transfer control.

Next, the configuration of the receiving circuit section of the accommodating section shown in FIG. 3 will be explained.

To explain the operation of FIG. 3, input data from a terminal or a transmission path is input to a buffer 421, the number of bytes is counted by a byte counter 423, and a packet of a predetermined byte length is sent to a packet assembling circuit 422 at a predetermined time interval.
A header (including information such as destination and source) supplied from the packet header table 425 is added to the packet by an adder circuit 429 and stored in the packet storage buffer 427. At this time, the up/down counter 426 is incremented.

The buffer stored in the packet accumulation buffer 427 is
It is read out and sent to the input bus by a transfer permission signal from the transfer control circuit 428 to the bus. At this time, the up/down counter 426 is counted down. Therefore,
The packet to be sent is 1 in the packet storage buffer 427.
When there is a packet, the up/down counter 426 outputs a count value of ``1'' or more, and the output is output as a packet presence/absence signal to the filter circuit section (41 in FIG. 2, which will be described later in FIG. 5). The transfer control circuit 428 to the bus is controlled by a control line included in the input bus (for packet data transfer).

Next, the operation of the embodiment of the configuration diagram of the transmitting circuit section of the accommodating section shown in FIG. 4 will be explained.

When transferring a packet from the bus control section to the storage section, a control line included in the output bus controls the packet input control circuit 436 from the bus, and its control output drives the packet accumulation buffer 434, and the packet is sent to the output bus. The collected packets are stored in the packet accumulation buffer 434.

Further, each time a packet is input, the packet storage amount monitoring circuit 435 receives a signal from the circuit 436 and counts the storage amount of the packet storage buffer 434. The packets accumulated in the packet accumulation buffer 434 are sequentially disassembled in the packet disassembly circuit 433, and the data portion is outputted to the buffer 431, from which the packet is sent out as output data to a terminal or a transmission line. A data transfer control circuit 432 to the terminal controls data transfer to the terminal,
When the transfer is performed, the packet storage amount monitoring circuit 435 is notified and the number of packets in the packet storage buffer 434 is monitored. Then, when a predetermined amount or more of packets are accumulated in the buffer 434, the bus control unit is notified.

Next, the configuration of the embodiment of the filter circuit of the storage section shown in FIG. 5 and the data formant on the acquisition control bus shown in FIG. 6 will be explained.

In FIG. 5, 30 represents the downstream collection control bus, and 31 represents the upstream collection control bus, on the right side (upstream side) when facing the diagram.
is connected to the next-stage storage section, and the bus control section B is connected beyond that. Further, a front-stage storage section is connected to the left side (downstream side) as viewed in the figure.

The collection control bus 30 is notified of an information collection command in the format shown in FIG.

A start code is set at the beginning, followed by the total number of storage units on the bus.

When the header detection circuit 411 detects the start code of this command from the collection control bus 30, it drives the accumulated information collection notification circuit 413 and notifies the receiving circuit section (FIG. 3).
The contents of the status information (presence or absence of transmitted packets) are stored in the memory circuit 4.
18 to execute the write operation.

The next information in the command, the total number of storage units, is pulled into the storage unit decrement circuit 412, which decrements the number (-1 calculation), inserts it again at the same position as the number of storage units, and sends it to the previous stage storage unit. .

In this way, when the data is sequentially transferred to each storage unit connected in series and reaches the final storage unit, the number of storage units in the command becomes “0”, and when it is detected that it is the final stage, the The accommodating unit then transmits a response in the data format shown in (■) in FIG. 6 to the upstream collection control bus 31.

The beginning of this is a response code, and after that, fixed-length blocks that combine each storage section number and data section (initially, no data is input) are provided for each storage section number,
This is the format with a delimiter added at the end. Note that the data contents of each storage section number are written in the corresponding storage section.

The final stage storage section stores the first data corresponding to the data of the first storage section number (number 0) and the status information (presence or absence of a transmission packet) written in the memory circuit 418 from the receiving circuit section (Fig. 3). Insert into position.

This operation is performed in the filter circuit section of each housing section. To explain in detail, each time a response code is detected in the solder detection circuit 415 of FIG. 5 and a subsequent combination of housing section number and data is detected. , self-position counting circuit 4
A counting output (+1) is outputted to 16, and the number of detected objects is counted by a counting circuit 416 at its own position. The counted value is compared with the own address set in the setting means 417, and if a match is detected, the memory circuit 418 is driven to output the written state information. As a result, each accommodating section sequentially executes the operation of writing the status information of the respective receiving circuit section at the data position of its own accommodating section number.

Next, an embodiment of the configuration of the collection control circuit section of the bus control section shown in FIG. 7 and an embodiment of the structure of the status information table of the bus control section shown in FIG. 8 will be described.

The collection control circuit section (64 in FIG. 2) collects the status information from each storage section explained in FIGS. 5 and 6 above via the collection control buses 30 (downstream) and 31 (upstream). The status information table (65 in FIG. 2) holds the collected status information and is used for transfer control of the switch unit.

In FIG. 7, when the timer circuit 641 generates a timeout output for a predetermined time, or when the delimiter detection circuit 645 detects the delimiter added at the end of the response from the storage unit, the accumulated information collection notification timing generation circuit 64
2 is activated. As a result, the start code of the command (■ in FIG. 6) is sent from the header sending circuit 643, and subsequently, the data of the total number of copies to be stored is sent to the setting circuit 644 for the number of copies to be accommodated.

After sending the command, when a response (■ in FIG. 6) is returned from the storage unit, the header detection circuit 646 detects the first response command. The following data, which is a combination of the storage unit number and data of each storage unit, is sequentially input to the delay circuit 647, and the storage unit number therein is stored in the addressing circuit 649, and at the timing when it is output from the delay circuit 647. The data portion is latched by data latch circuit 648.

Next, in FIG. 8, when the data and address (accommodation part number) are set in the data latch circuit 648 and address designation circuit 649 of FIG. Each address corresponding to (
The data launched into the data latch circuit 648 is written into the position corresponding to the number currently stored in the address designation circuit among the numbers (no-1 to nOm). When all the data corresponding to each storage part number included in the response is received,
The status information table 65 provides the latest status information of each storage section.

The status information table in FIG.
Information indicating the presence/absence of transfer packets collected from all storage units in the packet storage buffer 4 in Figure 3).
27 to the filter circuit), and if there is any one of the transmission request packets, it instructs the input bus control section to request the packet transfer.

At this time, the storage unit number and packet transfer destination address information are notified. To explain with a diagram, when a storage unit with transfer packet presence/absence in the table is detected, its address is detected and converted into a storage unit number by an encoder 652, latched by a latch circuit 651, and the packet is transferred. The presence/absence information is also encoded by the encoder 652 and output.

An embodiment of the configuration of the input bus control section of the bus control section shown in FIG. 9 will be described.

The input bus control section 61 extracts the packet from the storage section according to instructions from the status information table shown in FIG. 8, and transfers the packet to the target buffer on the switch side.

In FIG. 9, 613 is a packet header latch circuit that latches the packet header from the input bus, a controller 615 is a circuit that controls the input bus control unit and generates each timing signal, and a transfer timing generation circuit 616
is a circuit that receives the transfer timing information generated by the controller 615 based on the response information and outputs a timing signal (PKT-TRN) that adds a packet corresponding to the timing at which transfer is permitted to the request frame; The generation circuit 617 is a circuit that analyzes the packet header and generates a transfer request to the output bus control unit of the transfer destination, the receive packet buffer 618 is a buffer that holds the packet to be transferred, and the frame generation circuit 619 is a circuit that analyzes the packet header and generates a transfer request to the output bus control unit of the transfer destination. This is a circuit that generates a request frame by periodically assembling and adding packets depending on the transfer timing. In this way, the status information of the receiving circuit of each storage unit (presence of transfer request, storage unit number, and packet transfer destination) is sent from the input packet transfer to the packet switching control unit, which identifies the status of each storage unit. can do.

To explain the operation, when the packet presence/absence information and storage section number from the status information table (FIG. 8) are received by the storage section transfer start instruction circuit 610 and the storage section designation circuit 611, respectively, the transfer control circuit 612 discriminates the information. Then, the input start timing signal is output from the storage section transfer start instruction circuit 610 to the control bus 10 in the human-powered bus, and at the same time, the storage section designation circuit 6
11 outputs the accommodation section number to the control bus 11, and further outputs a transfer permission signal from the control bus 12. These control buses 10 to 12 are supplied to the storage section as the control bus of input bus 1, and when inputted to the reception circuit section (FIG. 3) of the storage section with the corresponding number, they are detected by the transfer control circuit 428. , causes the packet storage buffer 427 to send the packet to the input bus.

Packets input from the input bus are sent to the clock circuit 61.
The packet information is separated by a timing signal (HD-LATCH) from a controller 615 that operates based on a clock of 4 and stored in a packet header latch circuit 613, and the packet information is stored in a receive packet buffer 618.

Note that the clock circuit 614 is synchronized by a synchronization signal (SYNC), and this synchronization signal is also supplied to other sections (output bus control section, transfer buffer, packet exchange control section) to perform synchronous operations.

The packet header of the packet header latch circuit 613 is
The packet is analyzed by the transfer request generation circuit 617, and in response to the instruction signal (REQ-GEN) from the controller 615, the packet is transferred to the output bus control unit (62 in FIG. 1).
A transfer request representing the transfer request is generated.

Further, the packet is held in the reception buffer 618 until the transfer timing generating circuit 616 allows the transfer.

The controller 615 is notified of response information (response to the transfer request from the input bus control unit) from the paired output bus control unit (62 in FIG. 1, described later with reference to FIG. 10). This is analyzed to generate transfer timing information for the packets stored in the received packet buffer 7618, and to notify the transfer timing generation circuit 616. In response to this, the transfer timing generation circuit 616 generates a transfer permission timing signal (PK
In response to this, the frame generation circuit 619 reads the corresponding packet from the receiving packet pants 7618, assembles the information as a request frame (see FIG. 12), and sends the input packet transfer path (see FIG. 1). 7)
The data is sent to all transfer buffers (9 in FIG. 1) connected to this through the transfer buffer.

Such operations are repeated at regular intervals based on the clock signal from the clock circuit 614.

Next, the configuration of an embodiment of the output bus control section of the bus control section shown in FIG. 10 will be described.

The output bus control unit 62 performs control to extract packets from the transfer buffer 9 on the switch side and transfer the packets to a target storage unit.

In FIG. 10, a packet transmission control circuit 622 is a circuit that transfers the packet to the output bus when there is a packet in the transmission packet buffer, and a controller 624 is a circuit that controls the transmission packet transfer control unit and generates each timing signal. , a status detection circuit 625 is a circuit that monitors the transmission packet bus sofa and notifies the frame generation circuit of the input bus control unit of its status at any time; a transmission packet buffer 626 is a buffer that holds transferred packets;
The response launch circuit 627 is a circuit that stores response information of the response frame.

To explain the operation of FIG. 10, when the receiver 628 receives a response frame through the output packet transfer path, a timing signal (RES-LAT) is sent from the controller 624.
CH) stores the response information in the response frame.

This response information is sent to the controller of the input bus control section (FIG. 9). Also, packet information separated from the response frame is stored in the transmission packet pants 7626.

The status detection circuit 625 monitors the transmission packet buffer 626 and periodically notifies the frame generation circuit of the input bus control section (FIG. 9) of its load state as status information.

The packets stored in the transmission packet buffer are sent to the output bus 2 by the packet transmission control circuit 622. At this time, the storage unit number is set from the packet transmission control circuit 622 to the storage unit number address designation circuit 620, and the transfer timing generation circuit 621 is driven. The storage part number and transfer timing signal are the control line 20 of the output bus 2.
．． The packet input control circuit 43 is sent from the packet input unit 21 to the storage unit and is provided in the transmission circuit unit (FIG. 4) of the corresponding storage unit.
6 and the packet is input.

With the configuration of each part as described above, it is possible to efficiently collect status information from a large number of storage parts.

[Effects of the Invention] According to the present invention, in a high-speed bucket switching device using a matrix-type packet switch equipped with a bus control unit that pairs an input packet transfer path and an output packet transfer path,
The status of a large number of storage units connected to each bus control unit can be collected at high speed and without increasing the scale of hardware.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a connection configuration diagram of the housing section and bus control section, FIG. 3 is an embodiment configuration diagram of the reception circuit section of the housing section, and FIG. 4 is a transmission section diagram of the housing section. FIG. 5 is an example configuration diagram of the circuit section, and FIG. 6 is an example configuration diagram of the filter circuit of the housing section.
The figure shows the data format on the acquisition control bus, Figure 7 is an example configuration diagram of the acquisition control circuit section of the bus control unit, Figure 8 is an example configuration diagram of the status information table of the bus control unit, and Figure 9 is the input An example configuration diagram of the bus control section, FIG. 10 is an example configuration diagram of the output bus control section, and FIG. 11 is a basic configuration diagram of a conventional example.
FIG. 12 is a diagram showing the frame format on the packet transfer path of the switch. In Figure 1, 1.2: Input bus, and output bus 3: Collection control bus 4: Accommodation section 5: Terminal or transmission line 6: Bus control section 61: Input bus control section 62: Output bus control section 63: Collection Control unit 7: Input packet transfer path 8: Output packet transfer path 9: Transfer buffer (00 to MN) 10: Control bus 11: Packet exchange control unit

Claims (1)

[Claims] A plurality of bus control units (6) to which a pair of input packet transfer paths (7) and output packet transfer paths (8) are connected are provided, and the plurality of input packet transfer paths and the plurality of output packet transfer paths are connected to each other. Packet transfer paths are arranged in a grid pattern, and transfer buffers (
9), the two packet transfer paths are connected to each other via a control bus (10), and each transfer buffer is controlled by a packet exchange control unit (11) connected to a control bus (10), the packet switching device being connected to a terminal or a transmission path. An input/output bus (1, 2) through which a plurality of storage units (4) accommodating the packets transmits the packets.
and a collection control bus (3) that connects each storage unit in tandem to each bus control unit (6), and each storage unit (
4) transmits status information including the presence or absence of transmission packets to the collection control bus (3) to the bus control unit, and the bus control unit determines the status information of each storage unit collected from the collection control bus. , a data collection method for a packet switching device, characterized in that the packet switching control unit is notified of the data collection method.