JPH03101132A - Multilayer interconnection structure - Google Patents
Multilayer interconnection structureInfo
- Publication number
- JPH03101132A JPH03101132A JP23765989A JP23765989A JPH03101132A JP H03101132 A JPH03101132 A JP H03101132A JP 23765989 A JP23765989 A JP 23765989A JP 23765989 A JP23765989 A JP 23765989A JP H03101132 A JPH03101132 A JP H03101132A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- films
- interlayer insulating
- end faces
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 238000009413 insulation Methods 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数層の層間絶縁膜に形成されたコンタクト
ホールを介して下層配線と上層配線とが接続されている
多層配線構造に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multilayer wiring structure in which lower layer wiring and upper layer wiring are connected through contact holes formed in a plurality of interlayer insulating films. be.
本発明は、上記の様な多層配線構造において、複数層の
層間絶縁膜のうちの少なくとも−っの眉間絶縁膜のコン
タクトホールを囲む端面をこのコンタクトホールから離
間させることによって、上層配線の段差被覆性を良くす
る様にしたものである。In the multilayer wiring structure as described above, the present invention provides step coverage of the upper layer wiring by separating the end face surrounding the contact hole of at least one of the interlayer insulation films of the plurality of interlayer insulation films from the contact hole. It is designed to improve sex.
第２図は、抵抗負荷型ＭＯ３−３ＲＡＭのビット線との
コンタクト部及びその近傍を示している。FIG. 2 shows the contact portion with the bit line of the resistive load type MO3-3RAM and its vicinity.
即ち、転送用トランジスタのゲート配線つまりワード線
が、Ｓｉ基板１１上の第１層目の多結晶Ｓｉ膜１２によ
って形成されている。That is, the gate wiring of the transfer transistor, that is, the word line, is formed of the first layer polycrystalline Si film 12 on the Si substrate 11.
Ｓｉ基板１１の表面と多結晶Ｓｉ膜１２の上面とは、こ
れらの表面及び上面を酸化させて形成した５ｉＯｚ膜１
３によって覆われている。The surface of the Si substrate 11 and the upper surface of the polycrystalline Si film 12 are a 5iOz film 1 formed by oxidizing these surfaces and the upper surface.
Covered by 3.
５ｉＯｚ膜１３はＣＶＤで堆積させたＳｉｎ、膜１４に
よって更に覆われており、負荷用の抵抗素子を含む第２
層目の多結晶Ｓｉ膜１５がＳｉｎｇ膜１４上に形成され
ている。The 5iOz film 13 is further covered with a CVD-deposited Sin film 14, and a second
A multi-layer polycrystalline Si film 15 is formed on the Sing film 14.
多結晶Ｓｔ膜１５はＣＶＤで堆積させたＳｉｎｇ膜１６
によって覆われており、更にこのＳｉｎｇ膜１６はリフ
ロー膜であるＢＰＳＧ膜１７膜上７て覆われている。The polycrystalline St film 15 is a Sing film 16 deposited by CVD.
The Sing film 16 is further covered with a BPSG film 17 which is a reflow film.
Ｓｉｎ、膜１３．１４．１６及びＢＰＳＧ膜１７膜上７
Ｓｉ基板１１中のＮ″領域１８に達するコンタクトホー
ル１９が開孔されており、このコンタクトホール１９を
介して、ビット線であるＡＩＩ２Ｏ３Ｎ“領域１８とが
接続されている。Sin, film 13, 14, 16 and BPSG film 17 film 7
A contact hole 19 is formed in the Si substrate 11 to reach the N'' region 18, and the AII2O3N'' region 18, which is a bit line, is connected through the contact hole 19.
をなだらかにしても、コンタクトホール１９の垂直段差
が依然として大きく、Ａ７！膜２０の段差被覆性が良く
ない。Even if A7! is made smoother, the vertical step of contact hole 19 is still large. The step coverage of the film 20 is poor.
本発明による多層配線構造では、複数層の層間絶縁膜１
３．１４．１６．１７．２１のうちの少なくとも一つの
層間絶縁膜１４．１６のコンタクトホール１９を囲む端
面１４ａ、１６ａがこのコンタクトホール１９から離間
している。In the multilayer wiring structure according to the present invention, a plurality of interlayer insulating films 1
End surfaces 14a and 16a surrounding the contact hole 19 of at least one interlayer insulating film 14.16 among 3.14.16.17.21 are spaced apart from the contact hole 19.
ところで、多結晶Ｓｔ膜１２と多結晶Ｓｉ膜１５との間
で十分な眉間耐圧を確保するために、Ｓｉｎｇ膜１４に
は十分な膜厚が必要である。また、ＢＰＳＧ膜１７膜上
７結晶Ｓｉ膜１５ヘボロンやリンが拡散して抵抗素子の
抵抗値が減少するのを防止するために、５ｉＯｚ膜１６
にも十分な膜厚が必要である。Incidentally, in order to ensure sufficient glabellar breakdown voltage between the polycrystalline St film 12 and the polycrystalline Si film 15, the Sing film 14 needs to have a sufficient thickness. In addition, in order to prevent the resistance value of the resistance element from decreasing due to the diffusion of heboron and phosphorus on the 7crystalline Si film 15 on the BPSG film 17, a 5iOz film 16
A sufficient film thickness is also required.
従って、ＢＰＳＧ膜１７膜上７ローさせて、コンタクト
ホール１９に臨むＢＰＳＧＩＩ！１７の肩部〔作用〕
本発明による多層配線構造では、コンタクトホール１９
の垂直段差に対する層間絶縁膜１４．１６の端面１４ａ
、１６ａの垂直段差の寄与が少なく、従ってコンタクト
ホール１９の垂直段差が少ない。Therefore, the BPSG II! Shoulder portion of 17 [Function] In the multilayer wiring structure according to the present invention, the contact hole 19
The end surface 14a of the interlayer insulating film 14.16 with respect to the vertical step difference in
, 16a has a small contribution, and therefore the vertical step of the contact hole 19 is small.
以下、抵抗負荷型ＭＯ３−３ＲＡＭに適用した本発明の
一実施例を、第１図を参照しながら説明する。An embodiment of the present invention applied to a resistive load type MO3-3 RAM will be described below with reference to FIG.
本実施例は、ＳｉＯ□膜１３とＳｉＯ□膜１４との間に
３００人程度の厚さのＳｉ３Ｎ４膜２１が設けられてお
り、コンタクトホール１９を囲むＳｉＯ□膜１４．１６
の端面１４ａ、１６ａがこれらの端面１４ａ、１６ａの
垂直段差の３倍程度以上にまでコンタクトホール１９か
ら離間していることを除いて、第２図に示したー従来例
と実質的に同様の構成を有している。In this embodiment, an Si3N4 film 21 with a thickness of about 300 layers is provided between the SiO□ film 13 and the SiO□ film 14, and the SiO□ film 14, 16 surrounding the contact hole 19 is
The contact hole 19 is substantially the same as the conventional example shown in FIG. 2, except that the end surfaces 14a and 16a of the contact hole 19 are separated from the contact hole 19 by more than three times the vertical height difference between the end surfaces 14a and 16a. It has a structure.
Ｓｉ３Ｎ４膜２１は、減圧ＣＶＤによって堆積させる。The Si3N4 film 21 is deposited by low pressure CVD.
また、上述の様にＳｉＯ□膜１４．１６の端面１４ａ、
１６ａをコンタクトホール１９から離間させるには、上
述の様な寸法の開孔２２ａを有するマスク２２と緩衝フ
ン化水素酸とを用いて、ＢＰＳＣ膜１７の堆積前にＳｉ
ｎｇ膜１４．１６をエッチオフする。なお、５ｉＪ４膜
２１がこのエツチングのストッパとなる。In addition, as described above, the end surface 14a of the SiO□ film 14.16,
In order to separate the contact hole 16a from the contact hole 19, a mask 22 having an opening 22a having the above-mentioned dimensions and buffered hydrofluoric acid are used to remove Si before depositing the BPSC film 17.
The NG films 14 and 16 are etched off. Note that the 5iJ4 film 21 serves as a stopper for this etching.
この様な本実施例では、上述の様にＳｉＯ□膜１４．１
６の端面１４ａ、１６ａがこれらの端面１４ａ、１６ａ
の垂直段差の３倍程度以上にまでコンタクトホール１９
から離間しているので、ＳｉＯ□膜１４．１６の端面１
４ａ、１６ａの垂直段差の影響がコンタクトホール１９
には及ばない。In this embodiment, as described above, the SiO□ film 14.1 is
The end surfaces 14a, 16a of 6 are these end surfaces 14a, 16a.
The contact hole 19 is approximately three times the vertical height of the
Since it is spaced from the end face 1 of the SiO□ film 14.16
The effect of the vertical step difference between 4a and 16a is the contact hole 19.
It doesn't come close to that.
従って、コンタクトホール１９の垂直段差が少なく、Ａ
Ｉ！膜２０の段差被覆性が良い。また、ＢＰＳＧ膜１７
膜上７ ＋ ４５域１８等へのポロンやリンの拡散は、
５ｉＪｎ膜２１によって効果的に阻止される。Therefore, the vertical step of the contact hole 19 is small, and the
I! The film 20 has good step coverage. In addition, the BPSG film 17
The diffusion of poron and phosphorus into the 7 + 45 region 18 etc. on the membrane is as follows:
This is effectively blocked by the 5iJn film 21.
なお、ＳｉＯ□膜１４．１６をエッチオフした領域では
、多結晶Ｓｉ膜１２と多結晶Ｓｉ膜１５とが平面的に見
て離間しているので、これらの多結晶Ｓｉ膜１２と多結
晶Ｓｉ膜１５との間の層間耐圧を５ｉｆｚ膜１４によっ
て確保する必要がない。Note that in the region where the SiO□ film 14.16 is etched off, the polycrystalline Si film 12 and the polycrystalline Si film 15 are separated from each other when viewed in plan. There is no need to ensure the interlayer breakdown voltage between the film 15 and the 5ifz film 14.
本実施例ではりフロー膜としてＢＰＳＧ膜１７膜上７た
が、Ａｓ５Ｇ膜やＰＳＧ膜等を用いることもできる。In this embodiment, the BPSG film 17 was used as the beam flow film, but an As5G film, a PSG film, or the like may also be used.
また、本実施例はＳｉ基板１１中のＮ゛領域１８とＡＩ
Ｉ２Ｏ３の接続に本発明を適用したものであるが、半導
体基板上の異なる層の配線層同士の接続にも本発明を適
用することができる。Further, in this embodiment, the N' region 18 in the Si substrate 11 and the AI
Although the present invention is applied to the connection of I2O3, the present invention can also be applied to the connection between wiring layers of different layers on a semiconductor substrate.
である。It is.
本発明による多層配線構造では、コンタクトホールの垂
直段差が少ないので、上層配線の段差被覆性が良い。In the multilayer wiring structure according to the present invention, since there are few vertical steps in the contact hole, the step coverage of the upper layer wiring is good.
第１図及び第２図は本発明の夫々−実施例及び−従来例
の側断面図である。
なお図面に用いた符号において、
１３．１４−−−−・−−−３ｉＯ□膜１４ａ −−−
−−・・・−・一端面
１６−−−−−・−・−・−−−−−５ｉ ０２膜１６
ａ −−−−一端面1 and 2 are side sectional views of an embodiment of the present invention and a conventional example, respectively. In addition, in the symbols used in the drawings, 13.14-----3iO□ film 14a ---
------・One end surface 16--------・---・------5i 02 membrane 16
a ----- One end surface
Claims (1)
して下層配線と上層配線とが接続されている多層配線構
造において、 前記複数層の層間絶縁膜のうちの少なくとも一つの層間
絶縁膜の前記コンタクトホールを囲む端面がこのコンタ
クトホールから離間している多層配線構造。[Scope of Claims] In a multilayer wiring structure in which a lower layer wiring and an upper layer wiring are connected through contact holes formed in a plurality of layers of interlayer insulation films, at least one of the plurality of layers of interlayer insulation films is provided. A multilayer wiring structure in which an end surface of an interlayer insulating film surrounding the contact hole is spaced apart from the contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23765989A JPH03101132A (en) | 1989-09-13 | 1989-09-13 | Multilayer interconnection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23765989A JPH03101132A (en) | 1989-09-13 | 1989-09-13 | Multilayer interconnection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101132A true JPH03101132A (en) | 1991-04-25 |
Family
ID=17018603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23765989A Pending JPH03101132A (en) | 1989-09-13 | 1989-09-13 | Multilayer interconnection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101132A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6034492A (en) * | 1997-04-30 | 2000-03-07 | Nec Corporation | Motor-generator |
| JP2007288471A (en) * | 2006-04-17 | 2007-11-01 | Japan Radio Co Ltd | Radio device |
-
1989
- 1989-09-13 JP JP23765989A patent/JPH03101132A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6034492A (en) * | 1997-04-30 | 2000-03-07 | Nec Corporation | Motor-generator |
| JP2007288471A (en) * | 2006-04-17 | 2007-11-01 | Japan Radio Co Ltd | Radio device |
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