JPH0290076A - Inspecting apparatus - Google Patents

Abstract

PURPOSE:To make it possible to improve inspection efficiency by summing up defect occurring rates for every specified inspecting time. CONSTITUTION:A control part 2 controls a pattern generating part 5 through a bus line 3. A test signal (a) is outputted into burn-in boards 10 through each driver 12. The signal (a) which is inputted into each semiconductor device through the board 10 makes the semiconductor device perform a specified operation, and a test result signal (b) is outputted. The signal (b) is inputted into a comparator 13 and compared with a threshold value signal (t) from the generating part 5. The judged result signal (c) from the comparator 13 is sent into the control part 2 through the line 3. In the control part 2, the defect occurring rate per unit time in all boards is computed based on the judged result signals. The control part 2 sums up the defect occurring rates which are computed for every unit time in time series and computes the changing state for every detected time. As a result, the control part 2 judges the end of inspection when the defect occurring rate becomes less than a preset constant reference.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention comprises: 1. The present invention relates to testing of semiconductor devices such as C, LSI, etc., and particularly relates to a technique that is effective when applied to a so-called dynamic burn-in test performed by operating a semiconductor device.

[Conventional technology]

An example of this type of technology described is “19
1988 edition, VLSI manufacturing and testing equipment guidebook JP2
There are 25 to P232.

In the above-mentioned documents, various environmental test devices and their purposes are explained.

In general, in this type of inspection called reliability testing, a product (semiconductor device) is shipped from the manufacturer, delivered on the final day, operates as specified to the final user, and reaches the end of its product life. The aim is to simulate this at an accelerated pace and use it to prevent initial failures and improve subsequent product reliability.

As one of the above-mentioned tests, a so-called dynamic burn-in test is known, in which a power supply voltage and a clock are applied to a semiconductor device, the device is left in a heated environment for a certain period of time, and the failure rate thereafter is checked.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, since the test is performed in a heated environment under so-called acceleration time, it is difficult to determine whether the test is being performed under the optimal conditions for the target semiconductor device, especially when the test time is appropriate. There is no standard for determining whether or not this is the case, which results in an unnecessarily long inspection time, which is one of the causes of lower inspection efficiency of semiconductor devices during mass production.

The present invention has been made with a focus on the above-mentioned problems, and its purpose is to develop a technology that can improve inspection efficiency by understanding the optimal inspection time for testing individual types of semiconductor devices. It is about providing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief summary of typical inventions disclosed in this application is as follows.

That is, a signal pattern generation means for generating a test signal for the semiconductor device on the test board, an output data judgment means for inspecting the output signal from the semiconductor device, and a defect detection unit for each fixed inspection time based on the judgment result. This system also includes aggregation means for calculating the incidence rate.

[Effect]

According to the above-mentioned means, it is possible to total up the defective occurrence rate every fixed inspection time, pay attention to the change in the defective occurrence rate, and use the time point when the defective occurrence rate stabilizes at a constant state as a guideline for completion of the inspection.

Therefore, it is extremely easy to ascertain the inspection completion time for each individual type of semiconductor device, and it is possible to appropriately set the inspection time during mass production.

〔Example〕

FIG. 1 is a block diagram showing a schematic configuration of an inspection apparatus according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a change in defect occurrence rate according to this embodiment.

As shown in FIG. 1, the inspection apparatus 1 of this embodiment has a control section 2 that performs main control of the entire inspection apparatus 1, and this control section 2 is connected to a storage section 4 and a pattern pattern via a pass line 3. A generating section 5 and a power supply section 6 are connected. 7 in the same figure
The constant temperature bath shown in is equipped with a heater 8 as a heating means, and is controlled so that the burn-in board group 10 housed in the bath can be brought to a predetermined il and 1 condition.

The heating temperature of the heater 8 can be controlled by the control section 2 through the pass line 3.

A determination section 11 is provided outside the tank corresponding to the burn-in board group IO, and a driver 12 for outputting a test signal from the pattern generation section 5 to each burn-in board group 10 is provided in each determination 1fllll. The comparator 13 compares the test result output signal from the burn-in board group IO with the threshold signal from the pattern generation section 5, and the output from the comparator I3 is sent to the control section 2 through the pass line 3. It is configured to be operated manually.

Although not shown, the burn-in board group 1 in the thermostatic chamber 7
In addition to a power supply voltage and a test signal, clock signals and the like can also be applied to 0.

Further, a display device 14 and an external input/output device 15 such as a floppy disk drive are also connected to the pass line 3, so that data and test results can be displayed and stored.

Next, the inspection process according to this embodiment will be explained.

When a plurality of semiconductor devices are mounted on the burn-in board 10 and housed in the constant temperature oven 7, the heater 8 starts heating under the control of the control section 2, and the power supply section 6 connects the semiconductor devices on the burn-in board 10. Start supplying driving power to. At the stage when the voltage value of the driving power supply becomes stable, the control R2 controls the pattern generating section 5 through the pass line 3, and outputs the test (ff No. a) to the burn-in board 10 through the driver 12 of the determining section 11. The test signal a input to each semiconductor device through this burn-in board 10 causes the semiconductor device to perform a predetermined operation and output a test result signal S. This test result signal S The signal C is input to the comparator 13 and compared with the threshold signal t from the pattern generating section 5. The determination result signal C from the comparator 13 is sent to the H control section 2 through the path line 3.

The control unit 2 calculates the failure rate per unit time for the entire burn-in board 10 based on the determination result signal. The failure rate calculated in this way is stored at a predetermined address in the storage unit 40 through the pass line 3. Here, the unit time refers to the time (for example, 1 hour) between the previous detection time of the defect occurrence rate and the current detection time.

In this way, the control unit 2 calculates the defective occurrence rate for each unit time, totals this over time, and calculates the state of change for each detection time.

As a result, if the defect rate falls below a preset standard (point C shown in FIG. 2), the control unit 2
determines the end of the test, instructs the heater 8 to stop heating and the power supply unit 6 to stop applying the electric voltage R, and notifies the operator of this through the display device I4 such as a CRT.

At this time, the control unit 2 controls from the test start S to the test end E.
The total time until then is recorded on a recording medium (not shown) in the external input/output device 15.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment, a case has been described in which the end of the test is determined by the control unit 2, and the stopping of the heater 8, the power supply unit 6, etc. are automatically performed according to instructions from the control unit 2. may be displayed on the display device 14 or the like only when the failure rate falls below a preset certain standard, and the subsequent operations may be performed manually by the operator.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to an inspection device used in a so-called burn-in test, which is the field of use of the invention.
The present invention is not limited to this, and can be widely applied to other II environment test equipment.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, according to the present invention, it is possible to total up the defective occurrence rate for each fixed inspection time, pay attention to the change in the defective occurrence rate, and use the time when the defective occurrence rate stabilizes at a constant state as a guide for completion of the inspection. Therefore, it becomes extremely easy to grasp the inspection completion time for each individual type of semiconductor device, and it becomes possible to appropriately set the inspection time during mass production and realize efficient inspection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of an inspection apparatus 1 according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing a change in defect occurrence rate according to this embodiment. DESCRIPTION OF SYMBOLS 1... Inspection device, 2... Control part, 3... Pass line, 4... Storage part, 5... Pattern generation part, 6...
・Power supply unit, 7... Constant temperature chamber, 8... Heater, 10
... Burn-in board, 11... Judgment section, 12...
・Driver 13... Comparator, 14... Display device,
15...External input/output device.

Claims (1)

[Claims] 1. An inspection device that tests a plurality of semiconductor devices mounted on a test board while continuing to supply at least driving power to the semiconductor devices mounted on the test board. and a signal pattern generating means for generating a test signal using the semiconductor device, an output data determining means for inspecting an output signal from the semiconductor device, and a totalizing means for calculating a failure rate for each predetermined inspection time based on the result of the determination. , an inspection device that makes it easy to decide whether to continue or end the inspection based on the aggregated results. 2. The inspection apparatus according to claim 1, further comprising means for determining whether to continue or terminate the inspection based on the total result.