JPH0289419A - Cmos inverter circuit - Google Patents

Cmos inverter circuit

Info

Publication number
JPH0289419A
JPH0289419A JP63241304A JP24130488A JPH0289419A JP H0289419 A JPH0289419 A JP H0289419A JP 63241304 A JP63241304 A JP 63241304A JP 24130488 A JP24130488 A JP 24130488A JP H0289419 A JPH0289419 A JP H0289419A
Authority
JP
Japan
Prior art keywords
channel mos
ron
vol
source
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63241304A
Other languages
Japanese (ja)
Inventor
Yuji Kakizaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63241304A priority Critical patent/JPH0289419A/en
Publication of JPH0289419A publication Critical patent/JPH0289419A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain a circuit not causing malfunction by connecting other N- channel MOS transistor(TR) to a source of an N-channel MOS TR whose drain and source are connected to a power terminal and a ground terminal and connecting either the source or drain to an output terminal and the other to the power terminal.
CONSTITUTION: With a signal fed to an input terminal set to an H level, an N-channel MOS TR 1 is conductive, a P-channel MOS TR 2 is interrupted and its output level goes to an L level VOL. In such a case, an N-channel MOS TR 3 is energized and a gate voltage VG6 is expressed as VG6=R5/(R4+R5+ RON)×VDD, where RON is an on-resistance of the N-channel MOS TR 3. Assuming a threshold voltage of an N-channel MOS TR 6 as VT, when the resistance ratio of the resistors R4, R5 and RON is selected to obtain a relation of VT< VG6-VOL, the N-channel MOS TR 6 is turned off, its output voltage goes to a relation of VT≥VG6-VOL by undershoot thereby blocking the undershoot.
COPYRIGHT: (C)1990,JPO&Japio
JP63241304A 1988-09-27 1988-09-27 Cmos inverter circuit Pending JPH0289419A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63241304A JPH0289419A (en) 1988-09-27 1988-09-27 Cmos inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63241304A JPH0289419A (en) 1988-09-27 1988-09-27 Cmos inverter circuit

Publications (1)

Publication Number Publication Date
JPH0289419A true JPH0289419A (en) 1990-03-29

Family

ID=17072291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63241304A Pending JPH0289419A (en) 1988-09-27 1988-09-27 Cmos inverter circuit

Country Status (1)

Country Link
JP (1) JPH0289419A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430389A (en) * 1992-09-29 1995-07-04 Hitachi, Ltd. Output circuit with a current injection circuit including a reference voltage generator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5430389A (en) * 1992-09-29 1995-07-04 Hitachi, Ltd. Output circuit with a current injection circuit including a reference voltage generator

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