JPH0288241U - - Google Patents
Info
- Publication number
- JPH0288241U JPH0288241U JP16787188U JP16787188U JPH0288241U JP H0288241 U JPH0288241 U JP H0288241U JP 16787188 U JP16787188 U JP 16787188U JP 16787188 U JP16787188 U JP 16787188U JP H0288241 U JPH0288241 U JP H0288241U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- package
- ceramic package
- memory
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16787188U JPH0288241U (US20030157025A1-20030821-C00031.png) | 1988-12-26 | 1988-12-26 | |
| DE68921452T DE68921452T2 (de) | 1988-12-26 | 1989-12-22 | Keramisches Modul für Halbleiterspeicher. |
| EP19890313510 EP0376645B1 (en) | 1988-12-26 | 1989-12-22 | Ceramic package for memory semiconductor |
| US07/915,404 US5256901A (en) | 1988-12-26 | 1992-07-20 | Ceramic package for memory semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16787188U JPH0288241U (US20030157025A1-20030821-C00031.png) | 1988-12-26 | 1988-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0288241U true JPH0288241U (US20030157025A1-20030821-C00031.png) | 1990-07-12 |
Family
ID=15857628
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16787188U Pending JPH0288241U (US20030157025A1-20030821-C00031.png) | 1988-12-26 | 1988-12-26 |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0376645B1 (US20030157025A1-20030821-C00031.png) |
| JP (1) | JPH0288241U (US20030157025A1-20030821-C00031.png) |
| DE (1) | DE68921452T2 (US20030157025A1-20030821-C00031.png) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102004060367A1 (de) * | 2004-12-15 | 2006-06-29 | Infineon Technologies Ag | Chipbaustein und Verfahren zur Herstellung eines Chipbausteins |
| KR20200007545A (ko) * | 2018-07-13 | 2020-01-22 | 삼성전기주식회사 | 음향 공진기 패키지 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979468A (US20030157025A1-20030821-C00031.png) * | 1972-12-04 | 1974-07-31 | ||
| JPS57132343A (en) * | 1981-12-25 | 1982-08-16 | Hitachi Ltd | Manufacture of semiconductor device for memory |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4629824A (en) * | 1984-12-24 | 1986-12-16 | Gte Products Corporation | IC package sealing technique |
-
1988
- 1988-12-26 JP JP16787188U patent/JPH0288241U/ja active Pending
-
1989
- 1989-12-22 DE DE68921452T patent/DE68921452T2/de not_active Expired - Fee Related
- 1989-12-22 EP EP19890313510 patent/EP0376645B1/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4979468A (US20030157025A1-20030821-C00031.png) * | 1972-12-04 | 1974-07-31 | ||
| JPS57132343A (en) * | 1981-12-25 | 1982-08-16 | Hitachi Ltd | Manufacture of semiconductor device for memory |
Also Published As
| Publication number | Publication date |
|---|---|
| DE68921452T2 (de) | 1995-09-14 |
| EP0376645A2 (en) | 1990-07-04 |
| EP0376645B1 (en) | 1995-03-01 |
| EP0376645A3 (en) | 1990-10-17 |
| DE68921452D1 (de) | 1995-04-06 |
