JPH0286154A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0286154A
JPH0286154A JP23642388A JP23642388A JPH0286154A JP H0286154 A JPH0286154 A JP H0286154A JP 23642388 A JP23642388 A JP 23642388A JP 23642388 A JP23642388 A JP 23642388A JP H0286154 A JPH0286154 A JP H0286154A
Authority
JP
Japan
Prior art keywords
leads
package
groups
semiconductor chip
specified interval
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23642388A
Other languages
Japanese (ja)
Inventor
Hiroyuki Uchiyama
Satoshi Oguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23642388A priority Critical patent/JPH0286154A/en
Publication of JPH0286154A publication Critical patent/JPH0286154A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize miniaturization, and improve mounting density by dividing leads into two groups, stacking them at a specified interval so as not to come into contact with each other, and leading out the leads from a package in the above-mentioned state.
CONSTITUTION: Leads 12 are divided into two groups; these groups are stacked, via an insulating layer, at a specified interval so as not to come into contact with each other; a semiconductor chip 13 is fixed on a tab 11 and a part of lead 12a arranged on the same plane as the tab 11, via epoxy adhesive agent or the like; the bonding pad of the semiconductor chip 13 and the leads 12 are electrically connected by wires 14. The semiconductor chip 13 and its peripheral region are encapsulated by a package 15 composed of, e.g., epoxy resin, and from one side surface of the package 15, the leads 12a, 12b are led out in the state that a specified interval is kept.
COPYRIGHT: (C)1990,JPO&Japio
JP23642388A 1988-09-22 1988-09-22 Semiconductor device Pending JPH0286154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23642388A JPH0286154A (en) 1988-09-22 1988-09-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23642388A JPH0286154A (en) 1988-09-22 1988-09-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0286154A true JPH0286154A (en) 1990-03-27

Family

ID=17000536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23642388A Pending JPH0286154A (en) 1988-09-22 1988-09-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0286154A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791274B2 (en) 2004-01-07 2010-09-07 Panasonic Corporation LED lamp
US10323819B2 (en) 2015-02-15 2019-06-18 Beijing Universal Lanbo Technology Co., Ltd. LED display screen covers and LED displays

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7791274B2 (en) 2004-01-07 2010-09-07 Panasonic Corporation LED lamp
US8405307B2 (en) 2004-01-07 2013-03-26 Panasonic Corporation LED lamp
US10323819B2 (en) 2015-02-15 2019-06-18 Beijing Universal Lanbo Technology Co., Ltd. LED display screen covers and LED displays

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