JPH0284755A - Semiconductor element wiring structure - Google Patents
Semiconductor element wiring structureInfo
- Publication number
- JPH0284755A JPH0284755A JP23772688A JP23772688A JPH0284755A JP H0284755 A JPH0284755 A JP H0284755A JP 23772688 A JP23772688 A JP 23772688A JP 23772688 A JP23772688 A JP 23772688A JP H0284755 A JPH0284755 A JP H0284755A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- conductive layer
- insulating film
- contact hole
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000126 substance Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 10
- 239000004020 conductor Substances 0.000 abstract description 6
- 238000001312 dry etching Methods 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000000463 material Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子構造、特に配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor device structures, and particularly to wiring structures.
従来の半導体素子における配線構造は、第２図に示すよ
うに、第１の導電層１を埋込んだ第１の絶縁層１３と、
第２の導電層２を埋込んだ第２の絶縁層１２と第３の絶
縁層１１とを積層し、第１の導電層１に対するコンタク
トホール５を絶縁層１３に開口し、第２の導電層２に対
するコンタクトホール６を絶縁層１３．１２に開口した
のち、ＡＱなどの導電性材料７を用いて、第１及び第２
の導電層１，２を接続していた。As shown in FIG. 2, the wiring structure in a conventional semiconductor device includes a first insulating layer 13 in which a first conductive layer 1 is embedded;
A second insulating layer 12 in which a second conductive layer 2 is embedded and a third insulating layer 11 are laminated, a contact hole 5 for the first conductive layer 1 is opened in the insulating layer 13, and a second conductive layer 1 is formed. After contact holes 6 for layer 2 are opened in insulating layer 13.12, a conductive material 7 such as AQ is used to form the first and second
conductive layers 1 and 2 were connected.
ところで、上述のような従来構造では、２つの導電層１
，２を接続するために、２つのコンタクトホールが必要
であった。このため、コンタクトホール開口のためのプ
ロセスを実行する上で、各種のプロセスマージンや２つ
のコンタクトホール面積が必要となり、面積効率が悪い
という問題点があった。By the way, in the conventional structure as described above, two conductive layers 1
, 2, two contact holes were required. For this reason, various process margins and areas for two contact holes are required to carry out a process for opening a contact hole, resulting in a problem of poor area efficiency.
本発明の目的は上記課題を解決した半導体素子配線構造
を提供することにある。An object of the present invention is to provide a semiconductor element wiring structure that solves the above problems.
上記目的を達成するため、本発明の半導体素子配線構造
においては、半導体素子配線構造の２つの導電層が絶縁
膜で表裏に分離され、相互には接触していないが、互い
に交差しており、当該交差部分において前記絶縁膜を貫
通して表面側に位置する第１の導電層から裏面側の第２
の導電層まで到達する第３の導電性物質を具備するもの
である。In order to achieve the above object, in the semiconductor element wiring structure of the present invention, two conductive layers of the semiconductor element wiring structure are separated into front and back sides by an insulating film, do not contact each other, but cross each other, At the intersection, the first conductive layer passes through the insulating film and is located on the front side, and the second conductive layer on the back side.
The third conductive material reaches the conductive layer.
次に、本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
以下に、導電層としてｎ”−５ｉ、絶縁膜としてＳｉＯ
□、埋込み導電層としてＷを使用した一実施例を示す。Below, n''-5i is used as a conductive layer, and SiO is used as an insulating film.
□ shows an example in which W is used as the buried conductive layer.
第１図は本発明の概要を示す断面図である。第１図（ａ
）に２つの導電層の位置関係を示す。FIG. 1 is a sectional view showing an outline of the present invention. Figure 1 (a
) shows the positional relationship between the two conductive layers.
図においてまず、導電層１，２はｎ“−８ｉよりなり、
導電層１は５ｉｎ２よりなる絶縁層８の表面に形成され
、導電層２は絶縁層８の下面に露出して埋設され、絶縁
Ｍ８は他の絶縁層９上に積層されている。In the figure, first, conductive layers 1 and 2 are made of n"-8i,
The conductive layer 1 is formed on the surface of an insulating layer 8 made of 5in2, the conductive layer 2 is exposed and buried in the lower surface of the insulating layer 8, and the insulating layer M8 is laminated on another insulating layer 9.
したがって、導電層１及び導電層２は絶縁層８により分
離されている。また、導電層１の表面はＳｉＯ□よりな
る絶縁層１０で覆われている。しかし、この２つの導電
層１，２は上下関係の位置により交差しているものとす
る。第１図（ｂ）において、この交差点内の少なくとも
一個所に、ＰＲ工程とドライエツチング方法とを用いて
、絶縁層８にコンタクト孔３を開口する。このドライエ
ツチングは導電層２が露出した時点で終了させる。次に
、第１図（ｃ）に示すようにＳｉ上にはＷが堆積される
が、Ｓｉｎ、上にはＷが堆積されないＷ選択ＣＶＤ法（
第４８回応物学会１７Ｐ−Ｑ−１１，鉛末他、選択ｃｖ
ｏ −ｔ＋成長におけるＳｉ及びＨ２還元反応：参照）
を用いてコンタクト孔３にタングステン（Ｗ）４を埋込
む。コンタクト孔３内に埋込まれた導電性材料であるＷ
４を通して２つの導電層１，２は電気的に接続される。Therefore, conductive layer 1 and conductive layer 2 are separated by insulating layer 8. Further, the surface of the conductive layer 1 is covered with an insulating layer 10 made of SiO□. However, it is assumed that these two conductive layers 1 and 2 cross each other due to their vertical position. In FIG. 1(b), a contact hole 3 is opened in the insulating layer 8 at least at one location within this intersection using a PR process and a dry etching method. This dry etching is terminated when the conductive layer 2 is exposed. Next, as shown in FIG. 1(c), W is deposited on Si, but W is not deposited on Sin (W selective CVD).
48th Society of Applied Physics 17P-Q-11, lead powder, etc., selection cv
Si and H2 reduction reaction during o -t+ growth: see)
Tungsten (W) 4 is embedded in the contact hole 3 using a method. W, which is a conductive material embedded in the contact hole 3
The two conductive layers 1, 2 are electrically connected through 4.
以上実施例では、導電層としてｎ”ＳＬを使用したが、
ｐ” Ｓｉでも可能であるし、他の材料でもよい。In the above embodiments, n"SL was used as the conductive layer, but
It is possible to use p'' Si or other materials.
また、埋込み導電材料として、実施例ではＷを使用した
が、他の材料であってもよい。Further, although W is used as the embedded conductive material in the embodiment, other materials may be used.
以上のように本発明によれば、２つの導電層の接続にコ
ンタクト孔を１つ開口すれば良いため、２つのコンタク
トホールを開口していた従来構造に比べて面積効率を向
上できる効果を有する。As described above, according to the present invention, since it is only necessary to open one contact hole to connect two conductive layers, the area efficiency can be improved compared to the conventional structure in which two contact holes are opened. .
第１図（ａ）〜（ｃ）は本発明の一実施例の工程を工程
順に示す断面図、第２図は従来例を示す断面図である。
１．２・・・導電層 ３・・・コンタクト
孔４・・・タングステン ７・・・導電性材料８
．９．１０・・・絶縁層
（ａ）FIGS. 1(a) to 1(c) are cross-sectional views showing the steps of an embodiment of the present invention in order of process, and FIG. 2 is a cross-sectional view showing a conventional example. 1.2... Conductive layer 3... Contact hole 4... Tungsten 7... Conductive material 8
．． 9.10... Insulating layer (a)
Claims (1)
裏に分離され、相互には接触していないが、互いに交差
しており、当該交差部分において前記絶縁膜を貫通して
表面側に位置する第１の導電層から裏面側の第２の導電
層まで到達する第３の導電性物質を具備することを特徴
とする半導体素子配線構造。(1) Two conductive layers of a semiconductor device wiring structure are separated by an insulating film, and although they do not contact each other, they intersect with each other, and at the intersection, the insulating film is penetrated to the front side. A semiconductor device wiring structure characterized by comprising a third conductive substance that reaches from the first conductive layer located to the second conductive layer on the back side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23772688A JPH0284755A (en) | 1988-09-21 | 1988-09-21 | Semiconductor element wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23772688A JPH0284755A (en) | 1988-09-21 | 1988-09-21 | Semiconductor element wiring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284755A true JPH0284755A (en) | 1990-03-26 |
Family
ID=17019581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23772688A Pending JPH0284755A (en) | 1988-09-21 | 1988-09-21 | Semiconductor element wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284755A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260340A (en) * | 1986-05-06 | 1987-11-12 | Toshiba Corp | Manufacture of semiconductor device |
-
1988
- 1988-09-21 JP JP23772688A patent/JPH0284755A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62260340A (en) * | 1986-05-06 | 1987-11-12 | Toshiba Corp | Manufacture of semiconductor device |
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