JPH0282581A - Method of manufacture of semiconductor device and semiconductor device manufactured by the method - Google Patents

Method of manufacture of semiconductor device and semiconductor device manufactured by the method

Info

Publication number
JPH0282581A
JPH0282581A JP23558988A JP23558988A JPH0282581A JP H0282581 A JPH0282581 A JP H0282581A JP 23558988 A JP23558988 A JP 23558988A JP 23558988 A JP23558988 A JP 23558988A JP H0282581 A JPH0282581 A JP H0282581A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
film
layer
silicon
insulating
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23558988A
Inventor
Kazuhiro Komori
Toshiaki Nishimoto
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Abstract

PURPOSE: To prevent a field insulating film from being eroded by etchant efficiently by a method wherein an interlayer insulating film on a floating gate composed of a first layer polycrystalline silicon film is composed of a three-layer insulating film made of SiO2, Si3N4 and SiO2 built up at a low temperature.
CONSTITUTION: A first layer polycrystalline silicon film 8 is applied to the surface of a substrate 1 and, after n-type impurity ions are implanted, the parts of the first layer polycrystalline silicon film 8 in a MOS-FET region P1 of a memory-bit isolation region reading system and a high breakdown strength system MOS-FET region P2 are removed by dry-etching. Then an interlayer insulating film 9 composed of a three- layer structure made of SiO2, Si3N4 and SiO2 is built up at a low temperature. Therefore, the diffusion of the impurity ions implanted into the first layer polycrystalline silicon film 8 is suppressed and the deposition of the impurity near the boundary between the first layer polycrystalline silicon film 8 and a gate oxide film 6 is avoided. Further, as an Si3N4 film which is one component of the interlayer insulating film 9 serves as a protective film against etchant, a field insulating film 5 beneath the end part of the first layer polycrystalline silicon film 8 remaining in a memory cell region M is not eroded by etchant.
COPYRIGHT: (C)1990,JPO&Japio
JP23558988A 1988-09-19 1988-09-19 Method of manufacture of semiconductor device and semiconductor device manufactured by the method Pending JPH0282581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23558988A JPH0282581A (en) 1988-09-19 1988-09-19 Method of manufacture of semiconductor device and semiconductor device manufactured by the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23558988A JPH0282581A (en) 1988-09-19 1988-09-19 Method of manufacture of semiconductor device and semiconductor device manufactured by the method

Publications (1)

Publication Number Publication Date
JPH0282581A true true JPH0282581A (en) 1990-03-23

Family

ID=16988239

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23558988A Pending JPH0282581A (en) 1988-09-19 1988-09-19 Method of manufacture of semiconductor device and semiconductor device manufactured by the method

Country Status (1)

Country Link
JP (1) JPH0282581A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5158902A (en) * 1989-04-28 1992-10-27 Kabushiki Kaisha Toshiba Method of manufacturing logic semiconductor device having non-volatile memory
US5175120A (en) * 1991-10-11 1992-12-29 Micron Technology, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5158902A (en) * 1989-04-28 1992-10-27 Kabushiki Kaisha Toshiba Method of manufacturing logic semiconductor device having non-volatile memory
US5175120A (en) * 1991-10-11 1992-12-29 Micron Technology, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

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