JPH028230U - - Google Patents
Info
- Publication number
- JPH028230U JPH028230U JP8615288U JP8615288U JPH028230U JP H028230 U JPH028230 U JP H028230U JP 8615288 U JP8615288 U JP 8615288U JP 8615288 U JP8615288 U JP 8615288U JP H028230 U JPH028230 U JP H028230U
- Authority
- JP
- Japan
- Prior art keywords
- level
- inverter
- elements
- polarity
- driven
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 1
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案の一例の構成図、第２図はその
説明のための波形図、第３図は従来技術の説明の
ための図である。
１は入力信号源、２，４，５，９はＮ型素子、
３，６，７，８はＰ型素子、１０は出力端子であ
る。
FIG. 1 is a configuration diagram of an example of the present invention, FIG. 2 is a waveform diagram for explaining the same, and FIG. 3 is a diagram for explaining the prior art. 1 is an input signal source, 2, 4, 5, 9 are N-type elements,
3, 6, 7, and 8 are P-type elements, and 10 is an output terminal.
Claims (1)
ートに供給すると共に、 上記入力信号を上記第１のレベルで駆動される
第１のインバータに供給し、 このインバータ出力で第２のレベルで駆動され
る他の極性の素子からなるカレントミラー回路を
制御し、 このカレントミラー回路の出力側の素子と上記
一の極性の素子とを上記第２のレベルの電源間に
直列に接続し、 この直列回路の接続中点に得られる信号を上記
第２のレベルで駆動される第２のインバータに供
給して、 この第２のインバータより上記第２のレベルの
出力信号を取出すようにしたレベル変換回路。[Claims for Utility Model Registration] Supplying an input signal of a first level to the gate of an element of one polarity, and supplying the input signal to a first inverter driven at the first level; A current mirror circuit consisting of elements of another polarity driven at a second level by the inverter output is controlled, and the elements on the output side of this current mirror circuit and the elements of the one polarity are connected to the power source of the second level. A signal obtained at the midpoint of the connection of this series circuit is supplied to a second inverter driven at the second level, and the second inverter outputs the second level. A level conversion circuit that extracts signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8615288U JPH028230U (en) | 1988-06-29 | 1988-06-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8615288U JPH028230U (en) | 1988-06-29 | 1988-06-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH028230U true JPH028230U (en) | 1990-01-19 |
Family
ID=31310797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8615288U Pending JPH028230U (en) | 1988-06-29 | 1988-06-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH028230U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5537858U (en) * | 1978-09-01 | 1980-03-11 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083421A (en) * | 1983-10-13 | 1985-05-11 | Seiko Epson Corp | Level shifting circuit |
| JPS6269719A (en) * | 1985-09-24 | 1987-03-31 | Toshiba Corp | Level conversion logic circuit |
-
1988
- 1988-06-29 JP JP8615288U patent/JPH028230U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6083421A (en) * | 1983-10-13 | 1985-05-11 | Seiko Epson Corp | Level shifting circuit |
| JPS6269719A (en) * | 1985-09-24 | 1987-03-31 | Toshiba Corp | Level conversion logic circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5537858U (en) * | 1978-09-01 | 1980-03-11 | ||
| JPS5723442Y2 (en) * | 1978-09-01 | 1982-05-21 |