JPH027561A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH027561A JPH027561A JP63159658A JP15965888A JPH027561A JP H027561 A JPH027561 A JP H027561A JP 63159658 A JP63159658 A JP 63159658A JP 15965888 A JP15965888 A JP 15965888A JP H027561 A JPH027561 A JP H027561A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- conductivity type
- entire surface
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 230000003647 oxidation Effects 0.000 abstract 2
- 238000007254 oxidation reaction Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に読出し専用記憶装置
を含む半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device including a read-only memory device.
プログラム可能な半導体装置、例えば、読出し専用記憶
装置（以下、Ｐ ＲＯＭと称す）は、その用途から、特
に記憶容量の高密度１ヒと、確実にプログラムできるこ
とが望まれている。2. Description of the Related Art Programmable semiconductor devices, such as read-only memory devices (hereinafter referred to as PROMs), are desired to be reliably programmed, especially with a high density storage capacity, due to their uses.
第３図は従来の半導体装置の一例を説明するための半導
体チップの断面図である。第３図に示すように、Ｐ型シ
リコン基板１上にＮ型埋込層２を形成した後、基板全面
にＮ型エピタキシャル層３を堆積する。次に、Ｎ型エピ
タキシャル層３層上に酸化シリコン膜４を形成し、イオ
ン注入法により、選択的にベース領域５を形成する。次
に、ベース領域５上の酸化シリコンＭ４を選択的にベー
ス領域が露出するよう開口することにより開孔部を形成
する。次に、露出したベース領域表面を含む半導体基板
全面に多結晶シリコン膜９を形成し、イオン注入するこ
とにより、多結晶シリコンを介してエミッタ領域６を形
成する。次に、アルミニウム等から成る金属膜８を被着
し、選択エツチングすることによりＦＲＯＭを含む半導
体装置を形成していた。FIG. 3 is a cross-sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. As shown in FIG. 3, after forming an N-type buried layer 2 on a P-type silicon substrate 1, an N-type epitaxial layer 3 is deposited on the entire surface of the substrate. Next, a silicon oxide film 4 is formed on the three N-type epitaxial layers, and a base region 5 is selectively formed by ion implantation. Next, an opening is formed by selectively opening the silicon oxide M4 on the base region 5 so that the base region is exposed. Next, a polycrystalline silicon film 9 is formed over the entire surface of the semiconductor substrate including the exposed surface of the base region, and ions are implanted to form an emitter region 6 through the polycrystalline silicon. Next, a metal film 8 made of aluminum or the like is deposited and selectively etched to form a semiconductor device including a FROM.
書込みをする時は、金属膜８よりエミッタ領域６及びベ
ース領域５に過電流を印加して、逆バイアスされたエミ
ッタ・ベース領域を破壊し、短絡させることにより情報
を書込んでいた。When writing, information is written by applying an overcurrent from the metal film 8 to the emitter region 6 and the base region 5 to destroy the reverse biased emitter and base regions and short-circuit them.
上述した従来の半導体装置では、書込特性を安定にする
ために、印加する書込電流を上げる必要がある。このた
めには、書込回路を構成する素子が高電流に耐えうるよ
うに、素子のパタンを大きくする必要があり、半導体装
置の高集積化への支障となっていた。この問題点を解決
するためには、エミッタ領域６にコンタクトするための
開孔部の大きさを小さくして、開孔部に流れる電流密度
を上げる必要があるが、従来の半導体装置では、ホトレ
ジストを用いて形成する開孔部の直径は１μｍが限度で
、それ以上小さくすることができず、書込回路を構成す
る素子の高集積化ができないという欠点があった。In the conventional semiconductor device described above, it is necessary to increase the applied write current in order to stabilize the write characteristics. For this purpose, it is necessary to enlarge the pattern of the elements constituting the write circuit so that they can withstand high current, which has been an obstacle to achieving higher integration of semiconductor devices. In order to solve this problem, it is necessary to reduce the size of the opening for contacting the emitter region 6 and increase the current density flowing through the opening. However, in conventional semiconductor devices, photoresist The diameter of the opening formed using the method is limited to 1 μm, and cannot be made smaller than that, which has the disadvantage that it is impossible to achieve high integration of the elements constituting the write circuit.
本発明の目的は、エミッタ領域にコンタクトするための
開孔部の大きさを従来より小さくすることにより、高集
積化が可能な半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that can be highly integrated by making the size of an opening for contacting an emitter region smaller than before.
本発明の半導体装置は、一導電型半導体基板上に選択的
に設けられた逆導電型埋込層と、前記逆導電型埋込層上
に設けられた逆導電型のエピタキシャル層と、前記逆導
電型エピタキシャル層主表面上に設けられた一導電型ベ
ース領域と、前記一導電型ベース領域主表面上に設けら
れた逆導電型エミッタ領域と、前記逆導電型エピタキシ
ャル層、前記一導電型ベース領域及び前記逆導電型エミ
ッタ領域上に設けられた第１の絶縁膜と、前記第１の絶
縁膜に選択的に設けられた前記エミッタ領域に達する開
孔部と、前記開孔部側壁部に設けられな第２の絶縁膜と
、前記第２の絶縁膜及び前記開孔部上に設けられた電極
層とを含んで構成される。The semiconductor device of the present invention includes: a buried layer of an opposite conductivity type selectively provided on a semiconductor substrate of one conductivity type; an epitaxial layer of an opposite conductivity type provided on the buried layer of the opposite conductivity type; a base region of one conductivity type provided on the main surface of the epitaxial layer of one conductivity type, an emitter region of opposite conductivity type provided on the main surface of the base region of one conductivity type, the epitaxial layer of opposite conductivity type, and the base of one conductivity type. a first insulating film provided on the emitter region and the opposite conductivity type emitter region, an aperture selectively provided in the first insulating film reaching the emitter region, and a side wall of the aperture. The semiconductor device includes a second insulating film that is not provided, and an electrode layer that is provided on the second insulating film and the opening.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の半導体装置の第１の実施例を説明する
ための半導体チップの断面図である。第１図に示すよう
に、Ｐ型シリコン基板１上にＮ型埋込層２を形成した後
、基板全面にＮ型エピタキシャル層３を堆積する。次に
、Ｎ型エピタキシャル層３層上に酸化シリコン膜４を形
成し、イオン注入法により、選択的にベース領域５を形
成する。次に、ベース領域５上の酸化シリコン膜４を選
択的にベース領域が露出するよう開口することにより開
孔部を形成する６次に、開孔部を含む基板全面に３００
〜１５００人の膜厚の窒化シリコンからなる第２の絶縁
膜７を形成し、絶縁膜７全面を異方性エツチングにより
エッチバックを行なう。これにより、開孔部側壁部に第
２の絶縁膜７が残るため、開孔部の直径が小さくなる効
果がある。次に、露出したベース領域表面を含む半導体
基板全面に多結晶シリコン膜９を形成し、イオン注入す
ることにより、多結晶シリコン”を介してエミッタ領域
６を形成する。次に、例えば、アルミニウム電極８を被
着し、選択エツチングすることによりＰＲＯＭを含む半
導体装置を形成する。FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of a semiconductor device of the present invention. As shown in FIG. 1, after forming an N-type buried layer 2 on a P-type silicon substrate 1, an N-type epitaxial layer 3 is deposited on the entire surface of the substrate. Next, a silicon oxide film 4 is formed on the three N-type epitaxial layers, and a base region 5 is selectively formed by ion implantation. Next, an opening is formed by selectively opening the silicon oxide film 4 on the base region 5 so that the base region is exposed.
A second insulating film 7 made of silicon nitride is formed to have a thickness of 1,500 nm, and the entire surface of the insulating film 7 is etched back by anisotropic etching. As a result, the second insulating film 7 remains on the side wall of the opening, which has the effect of reducing the diameter of the opening. Next, a polycrystalline silicon film 9 is formed on the entire surface of the semiconductor substrate including the exposed base region surface, and ions are implanted to form an emitter region 6 through the polycrystalline silicon.Next, for example, an aluminum electrode 8 is deposited and selectively etched to form a semiconductor device including a PROM.
第２°図は本発明の半導体装置の第２の実施例を説明す
るための半導体チップの断面図である。第２図に示すよ
うに、第１の実施例と同様な工程により、開口部を含む
基板全面に３００〜１５００人の膜厚の窒化シリコン膜
からなる第２の絶縁膜７を形成した後、第１の実施例で
は酸化シリコン膜４が露出したところで異方性エツチン
グによるエッチバックを終了していたが、本実施例では
、更にエッチバックを続行し、開孔部に段差が生じるよ
うな構造にすることに特徴がある。これにより、第１の
実施例と同様な効果に加え、開孔部上に形成する多結晶
シリコン膜９及びアルミニウム電極８のステップカバレ
ッジが向上するという効果がある。FIG. 2 is a sectional view of a semiconductor chip for explaining a second embodiment of the semiconductor device of the present invention. As shown in FIG. 2, after forming a second insulating film 7 made of a silicon nitride film with a thickness of 300 to 1,500 wafers over the entire surface of the substrate including the opening, by the same process as in the first embodiment, In the first embodiment, the etch-back by anisotropic etching was completed when the silicon oxide film 4 was exposed, but in this embodiment, the etch-back was further continued to create a structure in which a step was formed in the opening. It is characterized by what it does. This has the effect of improving the step coverage of the polycrystalline silicon film 9 and aluminum electrode 8 formed over the opening in addition to the same effect as the first embodiment.
以上説明したように、本発明は、エミッタ領域にコンタ
クトするための開孔部の側壁部に更に第２の絶縁膜を形
成することにより、開孔部の大きさを小さくすることが
できる。従って、情報書込時に、弱い書込電流で印加し
ても、開孔部を通過する電流密度を上げることができ、
結果的に書込回路をｉ成する素子を小型化できるので、
半導体装置を高集積化することが可能となる効果がある
。As described above, in the present invention, the size of the opening can be reduced by further forming the second insulating film on the side wall of the opening for contacting the emitter region. Therefore, when writing information, even if a weak write current is applied, the current density passing through the aperture can be increased.
As a result, the elements that make up the write circuit can be made smaller.
This has the effect of making it possible to highly integrate semiconductor devices.
Ｎ型エピタキシャル層、４・・・酸化シリコン膜、５・
・・ベース領域、６・・・エミッタ領域、７・・・第２
の絶縁膜、８・・・アルミニウム電極、９・・・多結晶
シリコンやN-type epitaxial layer, 4... silicon oxide film, 5.
...Base region, 6...Emitter region, 7...Second
insulating film, 8...aluminum electrode, 9...polycrystalline silicon,
Claims (1)
込層と、前記逆導電型埋込層上に設けられた逆導電型の
エピタキシャル層と、前記逆導電型エピタキシャル層主
表面上に設けられた一導電型ベース領域と、前記一導電
型ベース領域主表面上に設けられた逆導電型エミッタ領
域と、前記逆導電型エピタキシャル層、前記一導電型ベ
ース領域及び前記逆導電型エミッタ領域上に設けられた
第１の絶縁膜と、前記第１の絶縁膜に選択的に設けられ
た前記エミッタ領域に達する開孔部と、前記開孔部側壁
部に設けられた第２の絶縁膜と、前記第２の絶縁膜及び
前記開孔部上に設けられた電極層とを含んで形成されて
いることを特徴とする半導体装置。an opposite conductivity type buried layer selectively provided on one conductivity type semiconductor substrate; an opposite conductivity type epitaxial layer provided on the opposite conductivity type buried layer; and an opposite conductivity type epitaxial layer provided on the main surface of the opposite conductivity type epitaxial layer. a base region of one conductivity type provided on the main surface of the base region of one conductivity type, an emitter region of opposite conductivity type provided on the main surface of the base region of one conductivity type, the epitaxial layer of opposite conductivity type, the base region of one conductivity type and the emitter of opposite conductivity type. a first insulating film provided on the region, an aperture selectively provided in the first insulating film reaching the emitter region, and a second insulating film provided on a side wall of the aperture. What is claimed is: 1. A semiconductor device comprising: a film; and an electrode layer provided on the second insulating film and the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63159658A JPH027561A (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63159658A JPH027561A (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH027561A true JPH027561A (en) | 1990-01-11 |
Family
ID=15698516
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63159658A Pending JPH027561A (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH027561A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8061771B2 (en) | 2007-07-25 | 2011-11-22 | Roho, Inc. | Supportive back overlay for wheelchair back |
-
1988
- 1988-06-27 JP JP63159658A patent/JPH027561A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8061771B2 (en) | 2007-07-25 | 2011-11-22 | Roho, Inc. | Supportive back overlay for wheelchair back |
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