JPH0272499U - - Google Patents
Info
- Publication number
- JPH0272499U JPH0272499U JP14915388U JP14915388U JPH0272499U JP H0272499 U JPH0272499 U JP H0272499U JP 14915388 U JP14915388 U JP 14915388U JP 14915388 U JP14915388 U JP 14915388U JP H0272499 U JPH0272499 U JP H0272499U
- Authority
- JP
- Japan
- Prior art keywords
- address
- section
- data
- correction
- stored
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図及び第２図はそれぞれ本考案の第１及び
第２の実施例を示すブロツク図、第３図は従来の
ＲＯＭ集積回路の一例を示すブロツク図である。
１……マスクＲＯＭ部、２，２Ａ，２Ｂ……読
出制御部、３，３Ａ〜３Ｎ……訂正アドレスＰＲ
ＯＭ部、４，４Ａ……訂正データＰＲＯＭ部、５
，５Ａ〜５Ｎ……比較器、６，６Ａ……訂正アド
レス書込部、７，７Ａ……訂正データ書込部。
1 and 2 are block diagrams showing first and second embodiments of the present invention, respectively, and FIG. 3 is a block diagram showing an example of a conventional ROM integrated circuit. 1...Mask ROM section, 2, 2A, 2B...Reading control section, 3, 3A to 3N...Correction address PR
OM section, 4, 4A... Correction data PROM section, 5
, 5A to 5N... Comparator, 6, 6A... Correction address writing section, 7, 7A... Correction data writing section.
Claims (1)
マスクＲＯＭ部と、このマスクＲＯＭ部に格納さ
れているデータに誤りがあるとき、この誤りデー
タが格納されているアドレスを書込んで記憶して
おく訂正アドレスＰＲＯＭ部と、前記誤りデータ
と対応する正しいデータを書込んで記憶しておく
訂正データＰＲＯＭ部と、前記訂正アドレスＰＲ
ＯＭ部に記憶されているアドレスと外部から入力
されるアドレス信号のアドレスとが一致したとき
一致信号を出力する比較器と、この比較器から一
致信号が出力されたときには前記訂正データＰＲ
ＯＭ部から前記アドレス信号のアドレスと対応す
る正しいデータを読出し、一致信号が出力されな
いときには前記マスクＲＯＭ部から前記アドレス
信号のアドレスのデータを読出す読出制御部と、
前記訂正アドレスＰＲＯＭ部に、前記マスクＲＯ
Ｍ部の誤りデータが格納されているアドレスを書
込む訂正アドレス書込部と、前記訂正データＰＲ
ＯＭ部に、前記誤りデータと対応する正しいデー
タを書込む訂正データ書込部とを有することを特
徴とするＲＯＭ集積回路。 A mask ROM section that stores predetermined data at each address, and a correction address that stores the address where the error data is stored when there is an error in the data stored in the mask ROM section. a PROM section, a correction data PROM section in which correct data corresponding to the error data is written and stored, and the correction address PR.
a comparator that outputs a match signal when the address stored in the OM section matches the address of the address signal input from the outside; and a comparator that outputs a match signal when the address stored in the OM section matches the address of the address signal input from the outside;
a read control unit that reads correct data corresponding to the address of the address signal from the OM unit, and reads data of the address of the address signal from the mask ROM unit when a match signal is not output;
The correction address PROM section includes the mask RO.
a correction address writing section for writing an address in which the error data of the M part is stored; and the correction data PR.
A ROM integrated circuit characterized in that the OM section includes a correction data writing section for writing correct data corresponding to the error data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14915388U JPH0272499U (en) | 1988-11-15 | 1988-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14915388U JPH0272499U (en) | 1988-11-15 | 1988-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0272499U true JPH0272499U (en) | 1990-06-01 |
Family
ID=31421123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14915388U Pending JPH0272499U (en) | 1988-11-15 | 1988-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0272499U (en) |
-
1988
- 1988-11-15 JP JP14915388U patent/JPH0272499U/ja active Pending
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