JPH0266959A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to connect upper wiring layers readily without the occurrence of imperfect contact on the contact part with a semiconductor substrate at a lower wiring layer by connecting the first upper wiring layer and the second upper wiring layer which is higher than the first layer at an upper region of a flat first contact layer on a first interlayer insulating film. CONSTITUTION:A recess part 16 is formed on the upper surface of a lower Al wiring layer 7. The recess part 16 is filled with a filling insulating film 19 so that the upper surface becomes approximately flat. An upper region of a contact 6 at a first interlayer insulating film 9 is made flat. A first upper Al wiring layer 10 is arranged on the first interlayer insulating film 9 so as to cross the upper region of the contact window 6. Then, the upper surface of the upper region of the contact 6 is also flattened. A second contact window 13 is formed on the upper region of the first contact window 6 at a second interlayer insulating film 12. A second upper Al wiring layer 14 is formed on the second contact window 13. The first upper Al wiring layer 10 is connected to the second upper Al wiring layer 14 through the second contact window 13.

Description

[Detailed Description of the Invention] [Summary] Regarding the wiring structure of a semiconductor device, particularly a semiconductor device having a multilayer wiring structure having three or more wiring layers, an upper wiring layer is formed on a contact portion of a lower wiring layer with a semiconductor substrate. The aim is to provide a multilayer wiring structure in which interlayer connections can be easily made without causing contact failure, and in a semiconductor device with a multilayer wiring structure having three or more wiring layers, the semiconductor substrate or the wiring layer A lower insulating film formed on a lower conductive base made of A first wiring layer having a recess formed in the upper region of the first contact window, the recess directly flattened with a filling insulating film, and formed on the first wiring layer disposed surface. Alternatively, a first upper wiring layer passing through the upper region of the first contact window via a first interlayer insulating film made of a plurality of layers and a second upper wiring layer further above the first, It has a structure in which interlayer connection is made in the upper region of the first contact window via a second contact window provided in a second interlayer insulating film formed between the second upper wiring layers.

[Industrial application field]

The present invention relates to a semiconductor device, and particularly to a wiring structure of a semiconductor device having a multilayer wiring structure having three or more wiring layers.

In a semiconductor IC or the like with a multilayer wiring structure having three or more wiring layers, the overlap between the contact portion of the lower wiring layer with the semiconductor substrate and the interlayer connection portion between the upper wiring layers constitutes the upper wiring layer. Induction of wire breakage due to poor coverage of the conductive film leads to a decrease in the reliability of the semiconductor IC, etc. (this is avoided because it restricts the degree of freedom in design and prevents the improvement of the degree of integration of the semiconductor device). was.

Therefore, in order to achieve higher integration of layers, a structure of a multilayer wiring part that can overcome the above-mentioned restrictions is desired.

[Conventional technology]

Using conventional multilayer wiring formation technology, the interlayer connection between the upper wiring layers in a three-layer aluminum (AI) wiring structure is performed on the contact portion of the lower wiring layer with the semiconductor substrate. The structure is as shown in the schematic sectional view shown in FIG.

In FIG. 2, 1 is a p-type silicon (Si) substrate, 2 is a field oxide film, 3 is an n°-type impurity diffusion region,
4 is an oxide film for impurity blocking, 5 is phosphosilicate glass (PS
G), etc., 6 is a first contact window,
7 is the lower AI wiring layer, 8 is the first hillock
ck) Prevention insulating film, 9 is the first interlayer insulating film, 10 is the first upper AI wiring layer, 11 is the second hillock prevention insulating film, 12 is the second interlayer insulating film, 13 is the second , 14 is a second upper wiring layer, and 15 is a covering insulating film.

That is, in the conventional structure, the first contact window 6 formed in the lower insulating film 5 is etched by isotropic dry etching means and anisotropic dry etching means in order to prevent poor coverage of the lower AI wiring layer 7. A lower layer A is formed on the contact window 6 to cover the contact window 6 by a sputtering method.
A first recess 16 having a shape corresponding to the contact window 6 and a depth corresponding to the sum of the lower insulating film 5 and the impurity blocking oxide film 4 is formed on the upper surface of the first wiring layer 7. .

Therefore, chemical vapor deposition (CVD) is applied to the lower layer.
The upper surface of the first interlayer insulating film 9 formed to cover the wiring N7 is formed on the upper surface of the first interlayer insulating film 9, as shown in the figure, due to the nature of vapor phase growth of the insulating film, in which more insulating film grows on the upper edge of the recess. 1
A second recess 17 having the same depth as the recess 16 and steeper side surfaces is formed, and a first upper Jii formed on the recess 17 by sputtering.
A third recess 18 having steeper side surfaces and the same depth as the second recess 17 is formed on the upper surface of the AI wiring layer 10 .

Therefore, in the third contact window 13 formed in the upper region of the first contact window 6 of the second interlayer insulating film 12 formed to cover the upper part of the first upper wiring layer 10, , the second interlayer insulating film 12, the second hillock prevention insulating film 11, the lower insulating film 5, and the impurity blocking oxide film 4 form a steep step of nearly 2 μm. The thickness of the side surface of the contact window 13 of the second upper wiring layer 14 formed thereon by sputtering becomes extremely thin due to poor step coverage of the sputtering method, resulting in disconnection or increased resistance. The second upper AI wiring layer 14 and the first upper AI wiring layer 1
This causes an interlayer contact failure between the two layers.

[Problem to be solved by the invention]

As described above, in the conventional structure, in the upper region of the first contact window 6 where the n+ type impurity diffusion region 3, that is, the semiconductor substrate and the lower wiring layer 7 are connected, When making an interlayer connection with the wiring layer 14, the steep and high step formed in the contact window 13 that performs the interlayer connection causes a poor interlayer connection due to poor coverage of the wiring layer, resulting in poor reliability of the semiconductor device. There was a problem that the flexibility was reduced, and as a result, interlayer connections between upper wiring layers in the area were avoided, reducing the degree of freedom in design and hindering the improvement of the degree of integration. SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring structure in which interlayer connections between upper wiring VANs can be easily made on a contact portion of a lower wiring layer with a semiconductor substrate without causing contact failure.

[Means to solve the problem]

The above problem is solved by exposing the lower conductive substrate surface of a lower insulating film formed on a lower conductive substrate made of a semiconductor substrate or wiring layer in a semiconductor device with a multilayer wiring structure having three or more wiring layers. a first wiring layer disposed over the first contact window and having a recess formed in an upper region of the first contact window;
The recess is directly and flatly filled with a filling insulating film, and the first contact is formed through a first interlayer insulating film formed of one or more layers formed on the first wiring layer arrangement surface. A first upper wiring layer passing through the upper region of the window and a second upper wiring layer further above are provided on a second interlayer insulating film formed between the first and second upper wiring layers. The problem is solved by a semiconductor device according to the invention in which an interlayer connection is made via a second contact window in the upper region of the first contact window.

[For production]

That is, in the present invention, the first
flattening the surface of the upper region of the contact window of the first interlayer insulating film formed on the first wiring layer by flatly filling the recess formed on the upper surface of the wiring layer with a filling insulating film; After that, in the upper region of the planarized first contact window on the first interlayer insulating film,
An interlayer connection is made between the first upper wiring layer passing through the upper region of the first contact window and the second upper wiring layer located higher therein.

In this way, the upper surface of the first interlayer insulating film on the first contact window is formed flat, so that the first and second The step formed on the inner surface of the second contact window formed on the first contact window of the second interlayer insulating film between the wiring layers is as small as the thickness of the second interlayer insulating film. Since there is a step difference, the second contact window formed on the second contact window
The coverage of the upper wiring layer is greatly improved.

Since the thickness of the second wiring layer on the side surface of the second contact window is ensured sufficiently, contact failure caused by interlayer connection between upper layer wirings on the contact portion of the lower wiring layer can be ensured. A decline in confidence is prevented.

Therefore, according to the present invention, the degree of freedom in design can be improved without impairing the reliability of a semiconductor device having a multilayer wiring structure of three or more layers.

〔Example〕

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to a schematic sectional view of an embodiment shown in FIG. 1.

In FIG. 1, 1 is, for example, a p-type Si substrate, 2 is an O7 field oxide film with a thickness of about 6,000 by selective oxidation, 3 is an n-type impurity diffusion region, and 4 is about 1,000 by thermal oxidation.
5 is a lower layer insulating film made of PSG or the like with a thickness of about 8,000 layers, 6 is the first contact window, 7 is a lower layer with a thickness of about 5,000 layers formed by sputtering. Wiring layer 8 is S formed by CVD method.
A first insulating film made of iO□ or the like with a thickness of about 1000 to 2000, and 9 made of PSG or the like with a thickness of 4000.
The first interlayer insulating film 10 has a thickness of about 7000 and is formed by sputtering.The first upper layer AIl wiring layer 11
12 is a second insulating film made of SiO□ or the like with a thickness of about 1000 to 2000, and 12 is a thickness 5 made of PSG or the like.
The interlayer insulating film 13 is a second contact window, and the second upper AIl wiring layer 15 with a thickness of about 1 μm formed by sputtering is, for example, a PSG and silicon nitride (si3Na) film. 16 is a recessed portion, and 19 is a filling insulating film made of, for example, 5 iOz.

In the structure according to the present invention, as shown in FIG. ) is filled with a filling insulating film 19 such that the upper surface thereof is almost flat, thereby forming the contact 6 of the first interlayer insulating film 9 that is formed to cover the formation surface of the lower AI wiring layer 7. Flatten the upper area.

Then, the contact window 6 is placed on the first interlayer insulating film 9.
A first upper JiAl wiring layer 10 is disposed across the upper region of the substrate. Since the upper region of the first contact 6 of the first interlayer insulating film 9 is flattened as described above, the upper surface of the upper region of the contact 6 of the first upper AI wiring layer 1o is also flattened. ing.

Next, a second interlayer insulating film 12 is formed to cover the formation surface of the first upper AI wiring layer 10, and an interlayer connection is made in the upper region of the first contact window 6 of the second interlayer insulating film 12. A second contact window 13 is formed. As described above, since the upper surface of the first upper AI wiring layer 10 in this region is flattened, the step formed in the second contact window 13 is equal to the thickness of the second interlayer insulating film 12. This corresponds to, for example, about 5,000 people, which would be a lower level difference.

Next, a second upper layer AI is formed on the second contact window 13.
A wiring layer 14 is formed, and interlayer connection between the first upper AI wiring layer 10 and the second upper AI wiring N14 is performed via the second contact window 13. At this time, as described above, the step formed in the second contact window 13 is
3, which corresponds to the thickness of the second interlayer insulating film 12 on which the contact window 12 is formed. Since the film thickness of the wiring layer is also ensured sufficiently, there is no occurrence of contact failure between the wiring layers due to poor coverage.

The filling insulating film 19 is formed by a coating insulating film method, an etch-back method, or the like.

In the method using a coated insulating film, for example, organosilanol (R-5t(Oll)4), which can be coated thickly without causing cracks, is used as a coated insulating film with methanol,
Using Tokyo Ohka OCD type 7 dissolved in a solvent such as propylene glycol monopropyl ether,
The above OCD is placed on the substrate on which the lower layer AI wiring N7 has been formed.
A coated insulating film called Type 7 is spin-coded to fill the recess 16 on the lower AI wiring layer 7, and a predetermined step airing is performed to decompose and evaporate R, that is, organic groups in the coated insulating film. Oxidize 5t(OH)i to form SiO□
A filling insulating film 19 is formed by filling the recess 16 flatly. Note that this coating and curing process is repeated if the recessed portion 16 is not sufficiently flattened.

In the etch-back method, the lower AI wiring layer 7
The four parts 16 are formed by the CVO method on the substrate on which the formation of the four parts 16 is completed.
The recess 16 is flattened within the recess 16 by forming a film of, for example, Sin, to a thickness that sufficiently fills the recess 16, applying a resist layer for flattening the upper surface thereon, and etching the entire surface using an anisotropic dry etching means. Fill in the above SiO□
A filling insulating film 19 made of a film is left to be formed.

Note that the structure of the present invention can of course be applied to multilayer wiring structures using conductors other than AI.

The present invention is also applied to the case where upper wiring layers are interlayer connected to each other on the interlayer connection portion between the wiring layers.

〔Effect of the invention〕

As described above, according to the present invention, contact failure in the interlayer connection when the upper wiring layers are connected to each other on the contact portion of the lower wiring layer with the semiconductor substrate is prevented, so that the lower wiring layer It becomes possible to perform interlayer connection between upper layer wirings on the base contact portion of the substrate, thereby improving the degree of freedom in designing semiconductor ICs and the like.

Therefore, the present invention is effective for increasing the degree of integration of semiconductor RCs and the like.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view of an embodiment of the present invention, and FIG. 2 is a schematic sectional view of a conventional structure. In the figure, 1 is a p-type Si substrate, 2 is a field oxide film, 3 is an n-type impurity diffusion region, 4 is an oxide film for impurity blocking, 5 is a lower insulating film, 6 is a first contact window, and 7 is a 1 wiring layer to the lower layer, 8 the first hillock prevention insulation film, 9 the first interlayer insulation film, 10 the first upper AI wiring layer, 11 the second hillock prevention insulation film, 12 the first hillock prevention insulation film. 13 is a second contact window, 14 is a second upper AI wiring layer, 15 is a covering insulating film, 16 is a recessed portion, and 19 is a filling insulating film. Figure 2: Dual cross-sectional view of the building

Claims (1)

[Claims] In a semiconductor device having a multilayer wiring structure having three or more wiring layers, a lower conductive substrate surface of a lower insulating film formed on a lower conductive substrate made of a semiconductor substrate or a wiring layer is provided. The recess of the first wiring layer is disposed over the exposed first contact window and has a recess formed in the upper region of the first contact window. The upper part of the first contact window is directly and flatly filled with a filling insulating film, and the upper part of the first contact window is filled through a first interlayer insulating film made of one or more layers formed on the first wiring layer disposed surface. A first upper wiring layer passing through the area and a second upper wiring layer further above the second upper wiring layer are formed in a second interlayer insulating film formed between the first and second upper wiring layers. A semiconductor device comprising an interlayer connection in an upper region of the first contact window via a contact window.