JPH0265364U - - Google Patents
Info
- Publication number
- JPH0265364U JPH0265364U JP14452788U JP14452788U JPH0265364U JP H0265364 U JPH0265364 U JP H0265364U JP 14452788 U JP14452788 U JP 14452788U JP 14452788 U JP14452788 U JP 14452788U JP H0265364 U JPH0265364 U JP H0265364U
- Authority
- JP
- Japan
- Prior art keywords
- light
- envelope
- view
- emitting
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000037431 insertion Effects 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図aは本考案の一実施例を示す正面透視図
、第1図bは同側面透視図、第1図cは同底面図
、第2図aは本考案素子の挿入例を示す断面図、
第2図bは同底面図、第2図cは同外観斜視図、
第3図aは従来例を示す正面透視図、第3図bは
同側面透視図、第3図cは同底面図、第4図aは
従来素子の挿入例を示す断面図、第4図bは同底
面図、第4図cは同外観斜視図である。 1……素子チツプ、4……外囲器、5……凸状
突起。
、第1図bは同側面透視図、第1図cは同底面図
、第2図aは本考案素子の挿入例を示す断面図、
第2図bは同底面図、第2図cは同外観斜視図、
第3図aは従来例を示す正面透視図、第3図bは
同側面透視図、第3図cは同底面図、第4図aは
従来素子の挿入例を示す断面図、第4図bは同底
面図、第4図cは同外観斜視図である。 1……素子チツプ、4……外囲器、5……凸状
突起。
Claims (1)
- 発光又は受光素子チツプを透光性樹脂外囲器で
被覆してなる光半導体素子において、上記外囲器
の背面中央付近に縦方向に凸状突起を設けたこと
を特徴とする光半導体素子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14452788U JPH0265364U (ja) | 1988-11-04 | 1988-11-04 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14452788U JPH0265364U (ja) | 1988-11-04 | 1988-11-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0265364U true JPH0265364U (ja) | 1990-05-16 |
Family
ID=31412317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14452788U Pending JPH0265364U (ja) | 1988-11-04 | 1988-11-04 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0265364U (ja) |
-
1988
- 1988-11-04 JP JP14452788U patent/JPH0265364U/ja active Pending