JPH0265153A - Semiconductor device - Google Patents

Abstract

PURPOSE:To set the width of a dicing line narrowly by making a mark region exist extendedly inside a semiconductor element adjacent to a dicing line, and providing a target mark and an electrode for characteristics evaluation in this region. CONSTITUTION:A mark region 9 is made to exist inside a semiconductor element 1 adjacent to a dicing line 4, and a target marks 5 and 6 and an electrode 8 for characteristics evaluation are provided in this region. According to this constitution, the dicing line 4 can be set narrowly regardless of the dimensions of the target marks 5 and 6 or the electrode 8 for characteristics evaluation, accordingly a wafer can be utilized effectively, and the interval between the dicing lines can be made constant, therefore automatization of the dicing also becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device equipped with a dicing line that separates a plurality of semiconductor elements included in a semiconductor wafer.

[Conventional technology]

FIG. 3 is a diagram showing a conventional semiconductor device equipped with dicing lines. Characteristic evaluation m; [! An example in which a shaded mark area is formed. (C) shows an example in which a part of the semiconductor element area is used as the mark area, so that the semiconductor element, dicing line, and mark area coexist. In these figures, (1) is a semiconductor element formed on a semiconductor wafer, in which various active elements and other elements are formed, an active area (2) in which a predetermined circuit is formed, and an active area (2) in which active elements and other elements are formed. The dotted lines in the figure indicate the boundaries of these circular areas.The surface of the semiconductor element (1) is normally It is coated with glass whose main component is silicon dioxide or silicon nitride. (a) is a dicing line formed vertically and horizontally between semiconductor elements to separate each semiconductor element, so that silicon is not exposed. (5) and (6) in Fig. 3(B) are various target marks provided for mask alignment of the semiconductor element (1), and the semiconductor element 1 among the many dicing lines. Mark area (7A) on a specific dicing line at a rate of 1 for every 2 or 6 pieces.
and is provided within this mark area.

As shown in Fig. 3 (II), these target marks are provided in various sizes, such as a large mark [5] with a large size and a small mark (6) with a small size, and are used to improve the resolution when aligning the mask. If the resolution is rough, the large mark ((5) is used; if the resolution is fine, the small mark (6) is used. Also, (8) is the same as the mark area ((5)).
7A) is used to evaluate the electrical characteristics of semiconductor wafers, especially when forming each semiconductor device T-(1), without removing them from the production line during semiconductor wafer manufacturing operations. It is possible to automatically evaluate the local electrical characteristics of the affected part. (7B) in FIG. 3(C) is a dedicated mark area formed by reusing a part of the semiconductor element area, and is separated from the semiconductor element (1) by the dicing line (width). A target mark +51 (61) or a characteristic evaluation electrode (8) similar to that in the case of .

[Problem to be solved by the invention]

Since conventional semiconductor devices were configured as described above,
In the case of Fig. 3 (Δ), the width of the dicing line can be the same as the width of the kerf of the dicing machine, but as shown in Fig. 3 CB>, there is a target mark in the dicing line (4). (If the mark area of the characteristic evaluation electrode (8) such as 51 (6) is formed, the width of the dicing line (4) is determined according to the widest mark, and the mark area ( Since the dicing line (4) including the mark area (7Δ) has a width like - over its entire length, the part of the dicing line including the mark area where no mark is formed is not effectively used and becomes a lost area. , as shown in FIG. 3(C), when a dedicated mark area is formed, the area that can be used as a semiconductor element decreases accordingly, and the ratio of the area of the semiconductor element to the entire semiconductor wafer decreases. There is a problem in that the number of semiconductor elements obtained from the semiconductor wafer decreases as the size of the semiconductor wafer decreases.

In addition, dicing is performed along the center line of each dicing line, but when dicing lines (4) with different widths are included as shown in FIG. 3(B) and <C>,
The dimension from the diced end face to the semiconductor element is different between the dicing line where the mark area was provided and the dicing line where the mark area was not provided, so the semiconductor element is measured based on the diced end face. In this case, the position of the T and pole to be bonded of the semiconductor element (1) fluctuates, and there is a problem that it takes time to align the bonding each time, making it difficult to automate dicing.

This invention was made to solve this problem, and by providing a mark area extending within the semiconductor element, all dicing lines are narrow as shown in FIG. 3(A). It is an object of the present invention to provide a semiconductor device that can effectively utilize a semiconductor wafer and also maintain constant spacing between dicing lines, thereby facilitating automation.

[Means to solve the problem]

In the semiconductor device according to the present invention, a mark region is formed extending from a dicing line into a semiconductor element adjacent to the mark region, and a target mark or a characteristic evaluation electrode is provided in this mark region. .

[For production]

In this invention, the mark region is not provided within the dicing line, but is formed extending from the dicing line into the semiconductor element adjacent thereto, and the target mark and the characteristic evaluation electrode are provided in this mark region. As a result, the width of the dicing line can be narrowed as shown in Figure 3 (A>) regardless of the dimensions of the target marker 1 mark or the characteristic evaluation electrode, and the spacing between the dicing lines can also be set narrowly. This is done so that it can be kept constant.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In this figure, elements (1) to (7) are the same as those of a conventional semiconductor device, so their explanation will be omitted. (9) is a mark area that constitutes the main part of the present invention, and is formed in such a way that it intersects with the dicing line (lυ) and extends into the non-active area (3) of the semiconductor element (1). In this case, a location is selected where the inactive area can be set relatively wide, as shown by the dotted line in FIG.

And the dicing line (41 is the semiconductor element both vertically and horizontally)
]) are provided at regular intervals along the periphery of the dicing machine, and the l+ is set to be narrow (for example, 90 p m ) corresponding to the width of the lily pad of the dicing machine in any part.

In addition, among the marks, the characteristics evaluation electrode (8) is small in size and smaller than the intermediate dicing line set as described above, so the mark area (
9), and there is no problem even if the - section is provided on the dicing line (/i) as shown in FIG.

FIG. 2 shows another embodiment of the present invention, in which the mark area (9) is provided at the intersection of the dicing lines (4), so that the corners of four semiconductor elements (1) that are in contact with this intersection are It is formed in such a way that it extends in each part. Also in this embodiment, the target mark (51 [6
By arranging the electrodes 1 and the characteristic evaluation electrodes (8) in a concentrated manner in the mark area (9), the dicing line (4) can be narrowed and the width of the dicing line (4) can be kept constant, making it possible to It can be used effectively. In this embodiment, since the intersection of the dicing lines of Aft fM is included in the mark region (9), the area extending within the non-active region (3) of the semiconductor element (1) is reduced.

〔Effect of the invention〕

As explained above, in this invention, a mark area is formed extending from a dicing line into a semiconductor element adjacent to the dicing line, and a target mark for alignment of semiconductor elements or a characteristic mark of a semiconductor wafer is formed in this mark area. Because the evaluation electrode is provided, the dicing line can be set without regard to the target mark or the dimensions of the characteristic evaluation electrode.
It can be set to a narrow width, and therefore the semiconductor wafer can be used effectively. Furthermore, since the intervals between the dicing lines can be kept constant, it is also possible to automate dicing.

[Brief explanation of the drawing]

FIG. 1 is an enlarged plan view showing an embodiment of the present invention, FIG. 2 is an enlarged plan view showing an embodiment of the pond of the invention, and FIG. 3 is an enlarged plan view showing a conventional semiconductor device. (B) is an example where only dicing lines are formed between semiconductor elements, (B) is an example where mark areas are formed within the dicing lines, (C)
) shows an example in which the mark area and the dicing line are left separate. In the figure, (1) is a semiconductor element, (2 is an active region, (
3) is the inactive area, (a) is the dicing line, f5)
f6) is Targera 1 ~ Mark, (7A) (7113
) (91 is the mark area, and (8) is the 7T:b pole for characteristic evaluation. The same reference numerals in each figure indicate the same or corresponding parts. Figure 2 Agent: Masuo Oiwa, patent attorney

Claims (1)

[Claims] A semiconductor wafer having a plurality of semiconductor elements, a dicing line provided between the semiconductor elements of the semiconductor wafer and separating each semiconductor element, a mark region extending from the dicing line into the semiconductor element adjacent to the dicing line, and A semiconductor device comprising a target mark for positioning the semiconductor element provided in the mark region or an electrode for characterizing the semiconductor wafer.