JPH0263358A - Erroneous detection preventing system for power fault in electronic exchange - Google Patents

Abstract

PURPOSE:To prevent the changeover in mistake through a detection signal from a power supply interruption detection circuit of each processor at application of power supply by providing a gate means inhibiting a detection signal of a connection circuit till an output from a timer means is generated. CONSTITUTION:A gate means 3 is driven in a prescribed time set to a timer means 2 after at the application of power. Since no output is generated from the gate means 3 even when a similar event to the interruption of power takes place in any of call processors CPR1-n and a main processor MPR before the prescribed time elapses and even when an output of power interruption means 61-61n, 5 goes to a high level 'H', an output to a changeover means 4 is inhibited. A high level 'H' signal is generated from the timer means 2 in a prescribed time elapses after a power supply on-detection means 1 produces an output, the gate means 3 is not subject to inhibition control and a power interruption detection signal from each processor is given to the changeover means 4 to allow the changeover. Thus, the drive of the changeover circuit in mistake by the power interruption detection circuit is prevented.

Description

[Detailed Description of the Invention] [Summary] A method for preventing false detection of power failure in electronic switching equipment that prevents detection of power failure when the system is powered on. The purpose of the present invention is to provide a method for preventing false detection of power failures in electronic exchanges, which prevents switching operations in electronic exchanges. In an electronic exchange equipped with a connection circuit in which power-off detection means are sequentially connected in series and when any one detects a power-off, the detection signal is transmitted to the main processor side one after another, the main processor is turned on. A power-on detection means for detecting and activated by a detection output of the power-on detection means,
The device comprises a timer means for generating an output after a predetermined time, a gate means for inhibiting a detection signal from the connection circuit until an output from the timer means is generated, and a switching means operated by the output of the gate means. Configure.

[Industrial Field of Application] The present invention relates to a method for preventing false detection of a power failure in an electronic exchange, which prevents detection of a power failure when the system is powered on.

The present applicant previously filed a patent application (Japanese Patent Application No. 117030/1982) titled "Electronic Switching System" regarding a technology for detecting power failures in electronic switching equipment.

According to the power failure detection technology for electronic exchanges proposed in the earlier application, even if the power is normally turned on when the system is powered on, it is possible to perform a failure detection operation as if a failure state has occurred by mistake. Since switching operations caused as a result of fault detection have a serious effect on the switching equipment, it is desirable to prevent erroneous fault detection operations.

[Prior Art] The structure of the electronic exchange proposed by the above-mentioned applicant is shown in FIGS. 3 to 5 as a conventional structure.

FIG. 3 is a block diagram of an electronic exchange, FIG. 4 is a block diagram of a power supply system, and FIG. 5 is a diagram showing a power failure detection circuit and interconnection arrangement.

FIG. 3 shows an electronic exchange with a dual multiprocessor configuration. Each prefecture of 0 system and 1 system has a main processor (MPR: management processor) and multiple call processors (CPR:
Processors of the same type are connected by an interprocessor communication bus. One of the two systems is set as the active system and the other as the standby system, but whenever a failure occurs in the active system, the standby system is switched to the active system to prevent service from going down. Further, the processor in each prefecture is equipped with a power-off detection circuit 31 as shown in FIG. 3, and the power-off detection circuits 31 in each prefecture are connected in series.

Conventionally, power is supplied to the processor using a commercial 100V or 200V power supply, as shown in the power supply system configuration diagram in Figure 4.
The rectifier 42 converts the DC voltage from the power supply 41 of V to -48V DC and supplies it to each processor, and then the necessary DC voltage, for example -5V, -12V, +12V, →-, is supplied to the power supply circuit 44 provided in each processor. It is converted to 5V etc.

As shown in FIGS. 4 and 5, the power-off detection circuit 31 detects the +5 power supply, which is one of the outputs of the power supply circuit of each processor. In the power failure detection circuit 31 shown in detail in FIG. 5, when the power supply of (1) +5 (3) becomes abnormal (cut), the output resistance of the output terminal becomes high impedance.

■When a high level "H" is input to input terminal a, a high level "H" is output to the output terminal, and vice versa, when a low level "L" is input manually, the output terminal becomes a low level "L". Output a signal.

■When the input terminal a is high impedance, the output terminal outputs a high level "H".

As a result, if the power-off detection circuits 31 of each processor are connected in series as shown in FIG.
When an abnormality occurs in the power supply of any of the call processing sensors in its own system, the system switching circuit 50 of the MPR) outputs the output of the power-off detection circuit 31 of that processor to "H" and sequentially transmits it through the connection line. The receiver will receive the coming 1H” signal,
As a result, if the system is the active system, the system switching circuit 50 immediately switches the system to become the standby system, and makes the other system the active system. Further, when the system switching circuit 50 detects a power-off state more than a predetermined number of times, it drives a re-beated emergency (REM) detection circuit, which will be described later.

FIG. 6 shows a block diagram of a PBX (private branch exchange) using the above-mentioned conventional technology.

In the PBX shown in the figure, the central office line from the public telephone exchange is connected to the main distribution board (M
Each TRK is connected to a switching network (denoted by SW) via a trunk (denoted by TRK). Further, a line extending to a telephone set for each subscriber is connected to the SW, and the SW is controlled by a control section.

The control unit is composed of a main processor CMPR) having a multiprocessor configuration shown in FIG. 3 and a plurality of call processors (CPR).

The revived emergency detection circuit (represented by REV detection circuit) 63 shown in the lower part of FIG.
MPR), which is activated when a failure that seriously affects the electronic exchange system repeatedly occurs.
Even when a detection signal from the power supply detection circuit 62, which is a series connection of power-off detection circuits of a plurality of processors shown in FIG. ) is driven.

When this REM detection circuit is driven, the system is put into a down state, and at the same time, the relay REM is driven and its contacts rem1 to rem2 are switched. As a result, the central office line from the public telephone exchange was switched to contact r.
eml, a line 60, and a contact r em 2 to connect to a telephone of a department that accepts calls in an emergency.

[Problems to be Solved by the Invention] However, when the power of the above conventional electronic exchange is turned on, the configuration is such that -48V is supplied from the rectifier 42 to the processor, as shown in the configuration of the power supply system in FIG.

When applying 48V to all processors at the same time from the rectifier 42, the power supply circuit of each processor reaches a predetermined voltage level by tracing a curve according to a time constant corresponding to each circuit constant. The time constant is not necessarily determined by all processors, and a phenomenon occurs in which high-level signals are generated from the power supply detection circuits of some processors in the power-off detection circuit 62 shown in FIG. 6, and the REM detection circuit 63 is driven. There was a problem.

Furthermore, when power is turned on to the system, a large amount of current (rush current) flows from the rectifier 42 to the power supply circuits 44 of a large number of processors, so the current capacity of the rectifier must be prepared to withstand a rush current larger than the load current in a steady state. There is a need to. However, since providing such a large capacity rectifier is costly, a smaller capacity rectifier is used. When using such a rectifier, the timing of power supply to each processor is varied in order to reduce rush current. In that case, the seventh
As shown in the figure, switches 5O2S1, .

However, if the timing of power-on to each processor is different, the power-off detection circuit 62 shown in FIG. 6 will generate a high-level signal indicating a power-off many times until all processors are powered on. , the REV detection circuit shown in FIG. 6 was driven and the system often went down.

As mentioned above, if a revived emergency is detected even though it is not an abnormal condition, the system will go down and the central office line will be switched to a specific telephone. There was a problem in that it required manpower and time. In the case of a switch such as a PBX, system power is turned on more frequently than in public telephone exchanges, although it varies depending on usage conditions (such as turning off the power on a holiday and starting it up after a holiday, or turning off the N source at night and starting it up the next morning). etc.), which increases the number of times the system goes down.

An object of the present invention is to provide a method for preventing erroneous detection of a power failure in an electronic exchange, which prevents erroneous switching operations based on detection signals from the power-off detection circuit of each processor when the system is powered on. shall be.

[Means to solve the problem] FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 is an MPR power-on detection means, 2 is a timer means, 3 is a gate means, 4 is a switching means, 5 is an MPR power-off detection means, and 61 to 61n are each call processor CPR1 to n.
represents a power-off detection means.

In the present invention, when the power-on detection means 1 of the main processor detects power-on, the timer means is started to control the gate means for a predetermined time, and the power-off detection means of each processor is turned off during the predetermined time. This prohibits the detection output from being supplied to the switching means.

[Operation] When the power of the main processor is turned on at the time of power-on of the system, the power-on detection means 1 generates an output, and the timer means 2 is set by the output and starts a timing operation. After a predetermined time set by the timer means 2, the gate means 3 is driven. Before the predetermined time is reached, a phenomenon similar to a power outage occurs in either of the call processors CPRI~n and the main processor MPR, and the outputs of the respective power outage detection means 61 to 61n, 5 go to a high level.
Since no output is generated from the gate means 3 even if it becomes "H", the output to the switching means 4 is prohibited. Power-on detection means 1
When a predetermined period of time has elapsed after the output is generated, the timer means 2
A high-level "H" signal is generated from the processor, the gate means 3 is no longer inhibited, and a power-off detection signal from each processor is applied to the switching means 4, enabling the switching operation.

As shown in FIG. 6, this switching means 4 switches and connects the central office line connected to the PBX from the trunk side of the exchange to a specific telephone set.

[Example] FIG. 2 shows a configuration diagram of an embodiment of the present invention.

21 in FIG. 2 is a power-on detection circuit, 22 is a counter, 2
3 represents an AND circuit, 24 a switching section, 25 a power-off detection circuit for the main processor MPR, and 261-26n power-off detection circuits for call processors CPR1-CPRn.

To explain the operation of the embodiment, when the power-on detection circuit 2I detects that the main processor is powered on, it generates a high-level "I(" output).

The counter 22 enters a counting active state when the high level "11" signal is input manually, and starts counting the clock manually (indicated by CLK). This counter 22 generates an overflow output when a preset count value is reached. As the count value, a value corresponding to a time of about 1 to 5 seconds is used.

Call Brossena CPR before counter 22 generates an output
1 to CPRn are supplied with power from the rectifier either simultaneously or sequentially at fixed time intervals (see Figure 4), and the + from each power supply circuit is supplied.
5■ occurs. The output terminals of the power-off detection circuits 261 to 26n of the power supply circuits of each of these processors are connected to the input side of the power-off detection circuit 25 of the main processor, and the output thereof is input to the AND circuit 23. ing. L7 Therefore, for example, even if the +5V output of the power supply circuit in a certain call processor rises with a delay, it will be supplied to the switching unit 24 as a power-off signal before the counter 22 outputs a high-level "H" signal. Not done.

The switching unit 24 includes a counter 241 and a station line switching circuit 242, and the counter 241 detects that the output from the AND circuit 23 has occurred a predetermined number of times or more, and uses the detected output to drive the station line switching circuit 242. Switch the PBX office line. If the output from the AND circuit 23 is less than a predetermined number of times, no output is generated and it is reset at a fixed time period.

[Effects of the Invention] According to the present invention, in an electronic exchange that turns on and off the power, it is possible to prevent the switching circuit from being erroneously driven by the power-off detection circuit when the power is turned on.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a conventional exchange, Fig. 4 is a block diagram of a power supply system, and Fig. 5 is a block diagram of a power supply system. FIG. 6 is a block diagram of a PBX (private branch exchange), and FIG. 7 is a block diagram for supplying power to each processor. In Figure 1, : MPR power-on detection means: Timer means: Gate means: Switching means: MPR power-off detection means

Claims (1)

[Claims] A main processor, a plurality of call processors, and power-off detection means (5, 61 to 61n) provided in each processor and detecting a power-off are sequentially connected in series, and any one of the and a connection circuit that sequentially transmits the detection signal to the main processor when the main processor detects a power-off, the power-on detection means (
1) and is activated by the detection output of the power-on detection means (1),
a timer means (2) that generates an output after a predetermined time; a gate means (3) that inhibits the detection signal of the connection circuit until the output from the timer means (2) is generated; and is operated by the output of the gate means. A method for preventing erroneous detection of a power failure in an electronic exchange, comprising: a switching means (4) for detecting a power failure;