JPH0255390A - Liquid crystal screen updating control circuit - Google Patents

Abstract

PURPOSE:To attain always determined image display even when an image generating device is a general one by updating pictures in a range capable of following the updating of input image data, and when the updating exceeds the range, displaying pictures without updating them. CONSTITUTION:A field memory circuit 1 writes an input image for one field based upon a dot clock and a horizontally/vertically synchronizing signal obtained from the image generating device side. When the succeeding field image to a field image stored in the circuit 1 is changed or not is detected by a change detecting circuit 2 in each dot. Then, the horizontal line of a dot position detected by the circuit 2 is detected by a change line detecting circuit 3 and pulse signals corresponding to the number of horizontal lines are generated. The pulse signals are counted up by a preset counter 4, field image data are written in a liquid crystal display panel 5 until the number of pulse signals reaches a preset value, and at the time of arriving at the preset value, the data writing is inhibited and the picture is updated. Even if general picture control is executed on the image generating device side, always determined image display can be attained.

Description

[Detailed Description of the Invention] [Regarding a simple matrix type LCD screen update control circuit in which the screen update operation on the machine side is slow, the screen display control on the image generation device side is made general-purpose to eliminate uncertain screen displays. A field memory circuit that writes human image data in one field and reads out the image data in the other field using a dot crotter, a horizontal synchronizing signal, and a vertical synchronizing signal, and a field memory circuit that reads out the image data in the other field using a dot crotter, a horizontal synchronizing signal, and a vertical synchronizing signal; a change detection circuit that detects for each dot whether or not the change has changed; a change line detection circuit that generates pulse signals equal to the number of horizontal lines including the change detection output of the change detection circuit according to the horizontal synchronization signal; The image data of the memory circuit is allowed to be written to the liquid crystal display panel until the signal is counted and reaches a preset value corresponding to the maximum number of updatable lines in one screen, and when the recent value is reached, the liquid crystal display is It consists of a preset counter that prohibits writing to the panel.

[Industrial Application Field] The present invention relates to a liquid crystal screen update control circuit, and particularly to a simple matrix type liquid crystal screen update control circuit in which the screen update operation is slow.

Generally, updating an LCD screen requires an erasing operation and a rewriting operation for each line, and updating the screen requires several hundred + ws.
Nematic/
There is a cholesteric phase transition method, but although it cannot perform high-speed display operation, it has high display contrast (transmittance), so it is used in large electronic OHPs used in conferences etc.
(Overhead Projector), and a screen display device using such a liquid crystal panel is desired.

[Prior art] In conventional low-speed LCD screen update control circuits, when the input screen from a high-speed image generation device such as a personal computer changes in a shorter time than the time required to update the screen, the entire screen is displayed on the LCD. Previously, the screen was refreshed each time.

[Problem to be solved by the invention]

With such conventional LCD screen update control circuits, the screen is updated before the LCD screen is completely displayed.
The displayed screen is not fixed, making it difficult to understand its contents.

In order to eliminate this problem, it is necessary to display a complete LCD screen by controlling the screen update interval from the image generating device such as a personal computer, but in the case of this method, general-purpose software must be used on the personal computer etc. The problem was that it became impossible to do so.

Therefore, an object of the present invention is to provide a general-purpose screen display control on the image generation device side in a simple matrix type liquid crystal screen update control circuit in which the screen update operation is slow, and to eliminate uncertain screen display.

[Means to solve the problem]

In order to achieve the above object, the liquid crystal screen update control circuit according to the present invention focuses on rewriting each horizontal line when updating the liquid crystal screen.

For this purpose, as shown in principle in FIG. 1, a field memory circuit 1 which manually writes image data in one field and reads out the image data in the other field according to clock pulses, horizontal synchronization signals and vertical synchronization signals. , a change detection circuit 2 that detects, dot by dot, whether or not the image data of the next field has changed with respect to the read image data; A changing line detection circuit 3 generates pulse signals equal to the number of lines, and a liquid crystal display of the image data of the memory circuit 1 counts the pulse signals until a preset value corresponding to the maximum number of updatable lines in one screen is reached. A recent counter 4 is provided which allows writing to the panel 5 and prohibits writing to the liquid crystal display panel 5 when the recent value is reached.

[Function] In the present invention shown in FIG. 1, the field memory circuit l stores one field of the input image based on a don't clock, horizontal synchronization signal, and vertical synchronization signal from the image generation device (not shown) side. Write.

Then, write 1 in the field memory circuit 1. A change detection circuit 2 detects for each dot whether or not the next field screen has changed with respect to the field screen that has been changed by α.

In the change line detection circuit 3, a horizontal line including the dot position of the change detection output detected dot by dot by the change detection circuit 2 is detected using a horizontal synchronizing signal, and pulse signals corresponding to the number of detected horizontal lines are generated.

Then, this pulse signal is counted by a preset counter 4 and compared with a preset value. This preset value corresponds to the maximum number of updatable lines in one screen, and the field screen data read from the memory circuit 1 can be written to the liquid crystal display panel 5 until this preset value is reached. When the preset value is reached, writing to the liquid crystal display panel 5 is prohibited.

In this way, rewriting of the liquid crystal display panel is prohibited only when the number of changed lines between adjacent field screens is greater than a preset value, thereby eliminating uncertain update screens.

〔Example〕

FIG. 2 shows an example of the configuration of the entire system incorporating the LCD screen update control circuit of the present invention shown in FIG.
1 is an image generating device such as a personal computer that sends out digital image signals 12 such as R, B, G signals and black and white signals; 13 is a screen display including a liquid crystal screen update control circuit 10 of the present invention and a liquid crystal display panel 5; It is a device.

FIG. 3 is a circuit diagram showing an embodiment of the LCD screen update control circuit 10 of the present invention conceptually shown in FIG. 1 and shown in FIG.
, line counter 21 , dot counter 22 , and T-FF
23, the field memory M includes a write terminal WR for writing image dot data from the image generator 11, and horizontal and vertical synchronization signals generated from the line counter 21 from the image generator 11. Terminal LA to input the line address of each dot data to be stored, terminal DA to input the dot address in one line generated from the dot counter 22 by the dot clock and horizontal synchronization signal from the image generator 11, It has a terminal RD for reading out image data, a terminal DC for receiving a dot clock, and a terminal RE for receiving a successive enable signal generated by the T-FF circuit 23 in response to a vertical synchronizing signal. In addition, the T-FF circuit 23 has Q output and ζ output alternately going to "H" level every time the vertical synchronization signal is input.
This is a circuit for causing the field memory M to perform a read operation and the liquid crystal display panel 4 to perform writing when the output is at the 1H" level. When the C output is at the "H" level, the field memory M performs the writing operation. The liquid crystal display panel 4 only performs operations and does not write data.Furthermore, the change detection circuit 2 is a mismatch detection circuit composed of an EOR gate.The change line detection circuit 3 clocks the mismatch detection output of the EOR gate 2. A launch circuit 24 that latches a D input fixed at "H" level (Vcc) as a signal and is reset by a horizontal synchronization signal, and an AND gate 25 that receives the Q output of this latch circuit 24 and the horizontal synchronization signal as input. It is made up of.

The preset counter 4 has a precent count value set by the preset switch 26 and the Q of the TFF 23.
When writing to the liquid crystal display panel 5, the AND gate 27 inputs the output and the vertical synchronization signal, and inputs the preset value of the present switch 26 to the liquid crystal display panel 5 via the inverter 2. field memory M.

Allow or prohibit writing (rewriting) of image data.

The operation of the embodiment shown in FIG. 3 will be explained below.

First, if we assume that the Q of the T-FF 23 is at "L" level and the field memory M is in the write enable state, the field memory M stores one frame of input image data.
The field is transferred to the terminal W at the memory address corresponding to the line address by the line counter 21 and the dot address by the dot counter 22 according to the dot clock.
Written via R.

After that, when the next vertical synchronization signal comes, the Q output of the T-FF 23 becomes "H" level, the field memory M becomes a read enable state, the liquid crystal display panel 5 becomes a write enable state, and the AND gate 27 The output also becomes "H" level, causing the preset counter 4 to read the preset value of the preset switch 26.

Therefore, the EOR gate 2 detects a mismatch between the image data for one field read from the field memory M and the image data for the next one field, and determines whether the latter has changed with respect to the former. Detects each dot.

This detection result is latched in the latch circuit 24, and when there is a change, the Q output becomes the "TI" level and the AND
is applied to gate 25. Since this launch output is reset every time a horizontal synchronizing signal arrives, the AND gate 25 sends pulse signals of a number corresponding to the number of lines to which donts that have changed between the previous field and the current field belong in each horizontal line. is given to the preset counter 4.

Therefore, the preset counter 4 counts this pulse signal, and since there is no overflow before reaching the precent value, the carry output is at "L'" level, and the liquid crystal display panel 5 is set to the write permission state via the inverter 28. The data read from the field memory M is written and updated and displayed.

When the preset value is reached, the carry output becomes "H" level, so the output of the inverter 28 becomes "L".
level, and writing to the liquid crystal display panel 5 is prohibited.

In addition, the Q output of the T-FF 23 is “H” on the liquid crystal display panel 5.
Since it is possible to write only when the level is
This is done every field, and the screen during that time does not change in the same way as when the preset value is exceeded.

Here, the preset value by the preset switch 26 is the rewriting time of one field of the personal computer - erasing time of the liquid crystal display (
This is the maximum number of lines that can be rewritten, which is determined from the relational expression: (usually about 100 seconds) -> - number of rewrite lines/required time for rewriting one line.

〔Effect of the invention〕

As described above, according to the LCD screen update control circuit of the present invention,
Compare adjacent field image data of input image data, count how many lines are updated, update the screen within the range that can follow the update of input image data, and when the range is exceeded, Since the screen display is configured to remain as it is, it is possible to keep track of the displayed screen at all times, and it is possible to eliminate unnecessary screens while the screen is being updated.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the principle of the LCD screen update control circuit according to the present invention, FIG. 2 is a schematic diagram showing the configuration of the entire system including the LCD screen update control circuit according to the present invention, and FIG. 1 is a circuit diagram showing an embodiment of a liquid crystal screen update control circuit according to the invention; FIG. In FIG. 1, 1... field memory circuit, 2... change detection circuit, 3... change line detection circuit, 4... recent counter, 5... liquid crystal display panel. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A field memory circuit (1) that writes input image data in one field and reads out the image data in the other field using a dot clock, a horizontal synchronization signal, and a vertical synchronization signal; a change detection circuit (2) that detects, dot by dot, whether or not the image data of the next field has changed; A changing line detection circuit (3) that generates a pulse signal, and a liquid crystal display of the image data of the memory circuit (1) until a preset value corresponding to the maximum number of updateable lines in one screen is reached by counting the pulse signal. A preset counter (4) that allows writing to the panel (5) and prohibits writing to the liquid crystal display panel (5) when the preset value is reached.
), and an LCD screen update control circuit.